UNPCKHPD
Usage: UNPCKHPD dest,src Modifies flags: None
Interleaved unpacking of the high double-precision floating-point values from the 'src' operand and the 'dest'.
Unpack and Interleave High Packed Double-Precision FP Values
UNPCKHPD xmm1,xmm2/m128 ; 66 0F 15 /r [WILLAMETTE,SSE2]
UNPCKHPD performs an interleaved unpack of the high-order data elements of the source and destination operands, saving the result in xmm1. It ignores the lower half of the sources.
The operation of this instruction is:
dst[63-0] := dst[127-64];
dst[127-64] := src[127-64].
The 'src operand can be an XMM register or a 128-bit memory location; the 'dest' operand is an XMM register.
EXAMPLE:
unpckhpd xmm1 Label
UD2
Usage: UD2 Modifies flags: None
Generates an invalid opcode. This instruction is provided for software testing to explicitly generate an invalid opcode. The opcode for this instruction is reserved for this purpose. Other than raising the invalid opcode exception, this instruction is the same as the NOP instruction.
Undefined Instruction
UD0 ; 0F FF [186,UNDOC]
UD1 ; 0F B9 [186,UNDOC]
UD2 ; 0F 0B [186]
UDx can be used to generate an invalid opcode exception, for testing purposes.(not implemented in RosAsm Assembler)
UD0 is specifically documented by AMD as being reserved for this purpose.(not implemented in RosAsm Assembler)
UD1 is documented by Intel as being available for this purpose.
UD2 is specifically documented by Intel as being reserved for this purpose. Intel document this as the preferred method of generating an invalid opcode exception.
All these opcodes can be used to generate invalid opcode exceptions on all currently available processors, but only UD2 is actually implemented in RosAsm assembler.
EXAMPLE:
ud2
UD1
Usage: UD1 Modifies flags: None
Undefined Instruction
UD0 ; 0F FF [186,UNDOC]
UD1 ; 0F B9 [186,UNDOC]
UD2 ; 0F 0B [186]
UDx can be used to generate an invalid opcode exception, for testing purposes. (not implemented in RosAsm Assembler)
UD0 is specifically documented by AMD as being reserved for this purpose. (not implemented in RosAsm Assembler)
UD1 is documented by Intel as being available for this purpose.
UD2 is specifically documented by Intel as being reserved for this purpose. Intel document this as the preferred method of generating an invalid opcode exception.
All these opcodes can be used to generate invalid opcode exceptions on all currently available processors, but only UD2 is actually implemented in RosAsm Assembler.
Example:
ud1
UD0
Usage: UDO Modifies flags: None
Undefined Instruction
UD0 ; 0F FF [186,UNDOC]
UD1 ; 0F B9 [186,UNDOC]
UD2 ; 0F 0B [186]
UDx can be used to generate an invalid opcode exception, for testing purposes.
UD0 is specifically documented by AMD as being reserved for this purpose. (not implemented in RosAsm Assembler)
UD1 is documented by Intel as being available for this purpose. (not implemented in RosAsm Assembler)
UD2 is specifically documented by Intel as being reserved for this purpose. Intel document this as the preferred method of generating an invalid opcode exception.
All these opcodes can be used to generate invalid opcode exceptions on all currently available processors, but only UD2 is actually implemented in RosAsm Assembler.
Example:
ud0
UCOMISS
Usage: UCOMISS src1,src2 Modifies flags: ZF PF CF OF SF AF
Unordered compare of the sngl-prec FP values in the low Dwords of 'src1' operand and the 'src2' operand and sets the ZF, PF, and CF flags in the EFLAGS register to the results,the OF, SF and AF flags are set to 0.
Unordered Scalar Single-Precision FP compare and set EFLAGS
UCOMISS xmm1,xmm2/m128 ; 0F 2E /r [KATMAI,SSE]
UCOMISS compares the low-order single-precision FP numbers in the two operands, and sets the ZF, PF and CF bits in the EFLAGS register. In addition, the OF, SF and AF bits in the EFLAGS register are zeroed out. The unordered predicate (ZF, PF and CF all set) is returned if either source operand is a NaN (qNaN or sNaN).
The UCOMISS instruction differs from the COMISS instruction in that it signals an SIMD floating-point invalid operation exception (#I) only when a source operand is an SNaN. The COMISS instruction signals an invalid operation exception if a source operand is either a QNaN or and SNaN. Source operand 1 is an XMM register; source operand 2 can be an XMM register or a 32 bit memory location.
EXAMPLE:
ucomiss xmm1 Label
UCOMISD
Usage: UCOMISD src1,src2 Modifies flags: ZF PF CF OF SF AF
Unordered compare of the dbl-prec FP values in the low Qwords of 'src1' operand and 'src2' operand, and sets the ZF, PF, and CF flags in the EFLAGS register to the results the OF, SF and AF flags in the are set to 0.
Unordered Scalar Double-Precision FP compare and set EFLAGS
UCOMISD xmm1,xmm2/m128 ; 66 0F 2E /r [WILLAMETTE,SSE2]
UCOMISD compares the low-order double-precision FP numbers in the two operands, and sets the ZF, PF and CF bits in the EFLAGS register. In addition, the OF, SF and AF bits in the EFLAGS register are zeroed out. The unordered predicate (ZF, PF and CF all set) is returned if either source operand is a NaN (qNaN or sNaN).
EXAMPLE:
ucomisd xmm1 Label
TEST
Usage: TEST dest,src Modifies flags: CF OF PF SF ZF (AF undefined)
Performs a logical AND of the two operands updating the flags register without saving the result.
Test Bits (notional bitwise AND)
TEST r/m8,reg8 ; 84 /r [8086]
TEST r/m16,reg16 ; o16 85 /r [8086]
TEST r/m32,reg32 ; o32 85 /r [386]
TEST r/m8,imm8 ; F6 /0 ib [8086]
TEST r/m16,imm16 ; o16 F7 /0 iw [8086]
TEST r/m32,imm32 ; o32 F7 /0 id [386]
TEST AL,imm8 ; A8 ib [8086]
TEST AX,imm16 ; o16 A9 iw [8086]
TEST EAX,imm32 ; o32 A9 id [386]
TEST performs a `mental' bitwise AND of its two operands, and affects the flags as if the operation had taken place, but does not store the result of the operation anywhere.
EXAMPLE:
Test eax ecx
SYSRET
Usage: SYSRET Modifies flags: None
Return From Operating System
SYSRET ; 0F 07 [P6,AMD,PRIV]
SYSRET is the return instruction used in conjunction with the SYSCALL instruction to provide fast entry/exit to an operating system.
The ECX register, which points to the next sequential instruction after the corresponding SYSCALL instruction, is copied into the EIP register.
Bits [63-48] of the STAR register specify the selector that is copied into the CS register.
Bits [63-48]+1000b of the STAR register specify the selector that is copied into the SS register.
Bits [1-0] of the SS register are set to 11b (RPL of 3) regardless of the value of bits [49-48] of the STAR register.
The CS and SS registers should not be modified by the operating system between the execution of the SYSCALL instruction and its corresponding SYSRET instruction.
For more information, see the SYSCALL and SYSRET Instruction Specification (AMD document number 21086.pdf).
Example:
sysret
SYSEXIT
Usage: SYSEXIT Modifies flags: None
Fast return to privilege level 3 user code.
Fast Return From System Call
SYSEXIT ; 0F 35 [P6,PRIV]
SYSEXIT executes a fast return to privilege level 3 user code. This instruction is a companion instruction to the SYSENTER instruction, and can only be executed by privilege level 0 code. Various registers need to be set up before calling this instruction:
SYSENTER_CS_MSR contains the 32-bit segment selector for the privilege level 0 code segment in which the processor is currently executing. (This value is used to compute the segment selectors for the privilege level 3 code and stack segments.)
EDX contains the 32-bit offset into the privilege level 3 code segment to the first instruction to be executed in the user code.
ECX contains the 32-bit stack pointer for the privilege level 3 stack.
SYSEXIT performs the following sequence of operations:
Adds 16 to the value in SYSENTER_CS_MSR and loads the sum into the CS selector register.
Loads the instruction pointer from the EDX register into the EIP register.
Adds 24 to the value in SYSENTER_CS_MSR and loads the sum into the SS selector register.
Loads the stack pointer from the ECX register into the ESP register.
Switches to privilege level 3.
Begins executing the user code at the EIP address.
For more information on the use of the SYSENTER and SYSEXIT instructions, see the Intel Architecture Software Developer's Manual, Volume 2.
EXAMPLE:
sysexit
SYSENTER
Usage: SYSENTER Modifies flags: None
Fast call to privilege level 0 system procedures.
Fast System Call
SYSENTER ; 0F 34 [P6]
SYSENTER executes a fast call to a level 0 system procedure or routine. Prior to executing the SYSENTER instruction, software must specify the privilege level 0 code. This instruction is a companion instruction to the SYSEXIT instruction.
Before using this instruction, various MSRs need to be set up:
SYSENTER_CS_MSR contains the 32-bit segment selector for the privilege level 0 code segment. (This value is also used to compute the segment selector of the privilege level 0 stack segment.)
SYSENTER_EIP_MSR contains the 32-bit offset into the privilege level 0 code segment to the first instruction of the selected operating procedure or routine.
SYSENTER_ESP_MSR contains the 32-bit stack pointer for the privilege level 0 stack.
SYSENTER performs the following sequence of operations:
Loads the segment selector from the SYSENTER_CS_MSR into the CS register.
Loads the instruction pointer from the SYSENTER_EIP_MSR into the EIP register.
Adds 8 to the value in SYSENTER_CS_MSR and loads it into the SS register.
Loads the stack pointer from the SYSENTER_ESP_MSR into the ESP register.
MSR Address
SYSENTER_CS_MSR 174H
SYSENTER_ESP_MSR 175H
SYSENTER_EIP_MSR 176H
Switches to privilege level 0.
Clears the VM flag in the EFLAGS register, if the flag is set.
Begins executing the selected system procedure.
In particular, note that this instruction des not save the values of CS or (E)IP. If you need to return to the calling code, you need to write your code to cater for this.
For more information, see the Intel Architecture Software Developer's Manual, Volume 2.
EXAMPLE:
sysenter