SLDT
Usage: SLDT dest Modifies flags: none
Stores the Local Descriptor Table (LDT) Register into the specified operand.
Store Descriptor Table Pointers
SGDT mem ; 0F 01 /0 [286,PRIV]
SIDT mem ; 0F 01 /1 [286,PRIV]
SLDT r/m16 ; 0F 00 /0 [286,PRIV]
SGDT and SIDT both take a 6-byte memory area as an operand: they store the contents of the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register) into that area as a 32-bit linear address and a 16-bit size limit from that area (in that order). These are the only instructions which directly use addresses, rather than segment/offset pairs.
SLDT stores the segment selector corresponding to the LDT (local descriptor table) into the given operand.
See also LGDT, LIDT and LLDT.
EXAMPLE:
sldt Label
SIDT
Usage: SIDT dest Modifies flags: none
Stores the Interrupt Descriptor Table (IDT) Register into the specified operand.
Store Descriptor Table Pointers
SGDT mem ; 0F 01 /0 [286,PRIV]
SIDT mem ; 0F 01 /1 [286,PRIV]
SLDT r/m16 ; 0F 00 /0 [286,PRIV]
SGDT and SIDT both take a 6-byte memory area as an operand: they store the contents of the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register) into that area as a 32-bit linear address and a 16-bit size limit from that area (in that order). These are the only instructions which directly use addresses, rather than segment/offset pairs.
SLDT stores the segment selector corresponding to the LDT (local descriptor table) into the given operand.
See also LGDT, LIDT and LLDT.
EXAMPLE:
sidt Label
SHUFPS
Usage: SHUFPS dest,src,select Modifies flags: None
Moves two of the four packed single-precision floating-point values from the 'dest' into the low quadword of the 'dest' operand; moves two of the four packed single-precision floating-point values from the 'src' into to the high quadword of the 'dest' operand. The 'select' operand determines which values are moved to the 'dest' operand.
Shuffle Packed Single-Precision FP Values
SHUFPS xmm1,xmm2/m128,imm8 ; 0F C6 /r ib [KATMAI,SSE]
SHUFPS moves two of the packed single-precision FP values from the destination operand into the low quadword of the destination operand; the upper quadword is generated by moving two of the single-precision FP values from the source operand into the destination. The select (third) operand selects which of the values are moved to the destination register.
The select operand is an 8-bit immediate: bits 0 and 1 select the value to be moved from the destination operand the low doubleword of the result, bits 2 and 3 select the value to be moved from the destination operand the second doubleword of the result, bits 4 and 5 select the value to be moved from the source operand the third doubleword of the result, and bits 6 and 7 select the value to be moved from the source operand to the high doubleword of the result.
EXAMPLE:
shufps xmm1 Label 2
SHUFPD
Usage: SHUFPD dest,src,select Modifies flags: None
Moves either of the two packed double-precision floating-point values from 'dest' into the low quadword of the 'dest' operand; moves either of the two packed double-precision floating-point values from the 'src' operand into to the high quadword of the 'dest' operand. The 'select' operand determines which values are moved to the 'dest'.
Shuffle Packed Double-Precision FP Values
SHUFPD xmm1,xmm2/m128,imm8 ; 66 0F C6 /r ib [WILLAMETTE,SSE2]
SHUFPD moves one of the packed double-precision FP values from the destination operand into the low quadword of the destination operand; the upper quadword is generated by moving one of the double-precision FP values from the source operand into the destination. The select (third) operand selects which of the values are moved to the destination register.
The select operand is an 8-bit immediate: bit 0 selects which value is moved from the destination operand to the result (where 0 selects the low quadword and 1 selects the high quadword) and bit 1 selects which value is moved from the source operand to the result. Bits 2 through 7 of the shuffle operand are reserved.
EXAMPLE:
shufpd xmm1 Label 1
SHRD
Usage: SHRD dest,src,count Modifies flags: CF PF SF ZF (OF,AF undefined)
Shifts 'dest' to the right 'count' times and the bit positions opened are filled with the least significant bits of the src.
Bitwise Double-Precision Shifts
SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386]
SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386]
SHLD r/m16,reg16,CL ; o16 0F A5 /r [386]
SHLD r/m16,reg32,CL ; o32 0F A5 /r [386]
SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386]
SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386]
SHRD r/m16,reg16,CL ; o16 0F AD /r [386]
SHRD r/m32,reg32,CL ; o32 0F AD /r [386]
SHLD performs a double-precision left shift. It notionally places its second operand to the right of its first, then shifts the entire bit string thus generated to the left by a number of bits specified in the third operand. It then updates only the operand according to the result of this. The second operand is not modified.
SHRD performs the corresponding right shift: it notionally places the second operand to the left of the first, shifts the whole bit string right, and updates only the first operand.
For example, if EAX holds x01234567 and EBX holds x89ABCDEF, then the instruction SHLD EAX,EBX,4 would update EAX to hold x12345678. Under the same conditions, SHRD EAX,EBX,4 would update EAX to hold xF0123456.
The number of bits to shift by is given by the third operand. Only the bottom five bits of the shift count are considered.
Example:
std
Do
mov al bl | and al 0F | add al '0'
On al > '9', add al 7
stosb | shrd ebx 4
Do_Loop
cld
SHR
Usage: SHR dest,count Modifies flags: CF OF PF SF ZF (AF undefined)
Shifts the destination right by 'count' bits with the current sign bit replicated in the leftmost bit. The Carry Flag contains the last bit shifted out.
Bitwise Logical Shifts
SHL r/m8,1 ; D0 /4 [8086]
SHL r/m8,CL ; D2 /4 [8086]
SHL r/m8,imm8 ; C0 /4 ib [186]
SHL r/m16,1 ; o16 D1 /4 [8086]
SHL r/m16,CL ; o16 D3 /4 [8086]
SHL r/m16,imm8 ; o16 C1 /4 ib [186]
SHL r/m32,1 ; o32 D1 /4 [386]
SHL r/m32,CL ; o32 D3 /4 [386]
SHL r/m32,imm8 ; o32 C1 /4 ib [386]
SHR r/m8,1 ; D0 /5 [8086]
SHR r/m8,CL ; D2 /5 [8086]
SHR r/m8,imm8 ; C0 /5 ib [186]
SHR r/m16,1 ; o16 D1 /5 [8086]
SHR r/m16,CL ; o16 D3 /5 [8086]
SHR r/m16,imm8 ; o16 C1 /5 ib [186]
SHR r/m32,1 ; o32 D1 /5 [386]
SHR r/m32,CL ; o32 D3 /5 [386]
SHR r/m32,imm8 ; o32 C1 /5 ib [386]
SHL and SHR perform a logical shift operation on the given source/destination (first) operand. The vacated bits are filled with zero.
A synonym for SHL is SAL. RosAsm will assemble either one to the same code.
The number of bits to shift by is given by the second operand. Only the bottom five bits of the shift count are considered by processors above the 8086.
Example:
std
Do
mov al bl | and al 0F | add al '0'
On al > '9', add al 7
stosb | shr ebx 4
Do_Loop
cld
SHLD
Usage: SHLD dest,src,count Modifies flags: CF PF SF ZF (OF,AF undefined)
Shifts 'dest' to the left 'count' times and the bit positions opened are filled with the most significant bits of 'src'.
Bitwise Double-Precision Shifts
SHLD r/m16,reg16,imm8 ; o16 0F A4 /r ib [386]
SHLD r/m16,reg32,imm8 ; o32 0F A4 /r ib [386]
SHLD r/m16,reg16,CL ; o16 0F A5 /r [386]
SHLD r/m16,reg32,CL ; o32 0F A5 /r [386]
SHRD r/m16,reg16,imm8 ; o16 0F AC /r ib [386]
SHRD r/m32,reg32,imm8 ; o32 0F AC /r ib [386]
SHRD r/m16,reg16,CL ; o16 0F AD /r [386]
SHRD r/m32,reg32,CL ; o32 0F AD /r [386]
SHLD performs a double-precision left shift. It notionally places its second operand to the right of its first, then shifts the entire bit string thus generated to the left by a number of bits specified in the third operand. It then updates only the operand according to the result of this. The second operand is not modified.
SHRD performs the corresponding right shift: it notionally places the second operand to the left of the first, shifts the whole bit string right, and updates only the first operand.
For example, if EAX holds x01234567 and EBX holds x89ABCDEF, then the instruction SHLD EAX,EBX,4 would update EAX to hold x12345678. Under the same conditions, SHRD EAX,EBX,4 would update EAX to hold xF0123456.
The number of bits to shift by is given by the third operand. Only the bottom five bits of the shift count are considered.
Example:
mov eax 2
mov ebx 2
shld eax ebx 2 ; eax = 8 ebx = 2
SHL
Usage: SHL dest,count Modifies flags: CF OF PF SF ZF (AF undefined)
Shifts the destination left by 'count' bits with zeroes shifted in on right. The Carry Flag contains the last bit shifted out.
Bitwise Logical Shifts
SHL r/m8,1 ; D0 /4 [8086]
SHL r/m8,CL ; D2 /4 [8086]
SHL r/m8,imm8 ; C0 /4 ib [186]
SHL r/m16,1 ; o16 D1 /4 [8086]
SHL r/m16,CL ; o16 D3 /4 [8086]
SHL r/m16,imm8 ; o16 C1 /4 ib [186]
SHL r/m32,1 ; o32 D1 /4 [386]
SHL r/m32,CL ; o32 D3 /4 [386]
SHL r/m32,imm8 ; o32 C1 /4 ib [386]
SHR r/m8,1 ; D0 /5 [8086]
SHR r/m8,CL ; D2 /5 [8086]
SHR r/m8,imm8 ; C0 /5 ib [186]
SHR r/m16,1 ; o16 D1 /5 [8086]
SHR r/m16,CL ; o16 D3 /5 [8086]
SHR r/m16,imm8 ; o16 C1 /5 ib [186]
SHR r/m32,1 ; o32 D1 /5 [386]
SHR r/m32,CL ; o32 D3 /5 [386]
SHR r/m32,imm8 ; o32 C1 /5 ib [386]
SHL and SHR perform a logical shift operation on the given source/destination (first) operand. The vacated bits are filled with zero.
A synonym for SHL is SAL. RosAsm will assemble either one to the same code.
The number of bits to shift by is given by the second operand. Only the bottom five bits of the shift count are considered by processors above the 8086.
Example:
shl eax 2 | mov ebx eax | shl ebx 2
add eax ebx ; (eax*4)+(eax*16) = eax * 20
SGDT
Usage: SGDT dest Modifies flags: none
Stores the Global Descriptor Table (GDT) Register into the specified operand.
Store Descriptor Table Pointers
SGDT mem ; 0F 01 /0 [286,PRIV]
SIDT mem ; 0F 01 /1 [286,PRIV]
SLDT r/m16 ; 0F 00 /0 [286,PRIV]
SGDT and SIDT both take a 6-byte memory area as an operand: they store the contents of the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register) into that area as a 32-bit linear address and a 16-bit size limit from that area (in that order). These are the only instructions which directly use addresses, rather than segment/offset pairs.
SLDT stores the segment selector corresponding to the LDT (local descriptor table) into the given operand.
See also LGDT, LIDT and LLDT.
EXAMPLE:
sgdt Label
SFENCE
Usage: SFENCE Modifies flags: None
Performs a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction.
Store Fence
SFENCE ; 0F AE /7 [KATMAI]
This serialization guarantees that all memory writes before the SFENCE instruction are visible before any writes after the SFENCE instruction. SFENCE is ordered respective to other SFENCE instruction, MFENCE, any memory write and any other serializing instruction (such as CPUID).
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The SFENCE instruction provides a performance-efficient way of insuring store ordering between routines that produce weakly-ordered results and routines that consume this data.
SFENCE uses the following ModRM encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 111B
R/M (2:0) = 000B
All other ModRM encodings are defined to be reserved, and use of these encodings risks incompatibility with future processors.
See also LFENCE and MFENCE.
EXAMPLE:
sfence