PSHUFD
Usage: PSHUFD dest,src,order Modifies flags: None
Copies doublewords from 'src' (second operand) and inserts them in the 'dest' (first operand) at the locations selected with the order operand (third operand).
Shuffle Packed Doublewords
PSHUFD xmm1,xmm2/m128,imm8 ; 66 0F 70 /r ib [WILLAMETTE,SSE2]
PSHUFD shuffles the doublewords in the source (second) operand according to the encoding specified by imm8, and stores the result in the destination (first) operand.
Bits 0 and 1 of imm8 encode the source position of the doubleword to be copied to position 0 in the destination operand. Bits 2 and 3 encode for position 1, bits 4 and 5 encode for position 2, and bits 6 and 7 encode for position 3. For example, an encoding of 10 in bits 0 and 1 of imm8 indicates that the doubleword at bits 64-95 of the source operand will be copied to bits 0-31 of the destination.
EXAMPLE:
pshufd xmm1 Label 2
PSADBW
Usage: PSADBW dest,src Modifies flags: None
Computes the absolute value of the difference of 8 unsigned byte integers from the 'src' (second operand) and from the 'dest' (first operand). These 8 differences are then summed to produce an unsigned word integer result that is stored in the 'dest' operand.
Packed Sum of Absolute Differences
PSADBW mm1,mm2/m64 ; 0F F6 /r [KATMAI,MMX]
PSADBW xmm1,xmm2/m128 ; 66 0F F6 /r [WILLAMETTE,SSE2]
PSADBW The PSADBW instruction computes the absolute value of the difference of the packed unsigned bytes in the two source operands. These differences are then summed to produce a word result in the lower 16-bit field of the destination register; the rest of the register is cleared. The destination operand is an MMX or an XMM register. The source operand can either be a register or a memory operand.
EXAMPLE:
psadbw xmm1 Label
PREFETCHh
Usage: PREFETCHh src Modifies flags: None
Fetches the line of data from memory that contains the byte specified with the 'src' operand to a location in the cache hierarchy specified by a locality hint.
Prefetch Data Into Caches
PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2
PREFETCHNTA m8 ; 0F 18 /0 [KATMAI]
PREFETCHT0 m8 ; 0F 18 /1 [KATMAI]
PREFETCHT1 m8 ; 0F 18 /2 [KATMAI]
PREFETCHT2 m8 ; 0F 18 /3 [KATMAI]
The PREFETCHh instructions fetch the line of data from memory that contains the specified byte. It is placed in the cache according to rules specified by locality hints h:
The hints are:
T0 (temporal data) - prefetch data into all levels of the cache hierarchy.
T1 (temporal data with respect to first level cache) - prefetch data into level 2 cache and higher.
T2 (temporal data with respect to second level cache) - prefetch data into level 2 cache and higher.
NTA (non-temporal data with respect to all cache levels) - prefetch data into non-temporal cache structure and into a location close to the processor, minimizing cache pollution.
This instruction is merely a hint and does not affect program behavior. If executed, this instruction moves data closer to the processor in anticipation of future use. The implementation of prefetch locality hints is implementation - dependent, and can be over-loaded or ignored by a processor implementation. The amount of data prefetched is also processor implementation-dependent. It will, however, be a minimum of 32 bytes.
Note that this group of instructions doesn't provide a guarantee that the data will be in the cache when it is needed. For more details, see the Intel IA32 Software Developer Manual, Volume 2.
EXAMPLE:
prefetchnta Label |prefetcht0 Label |prefetcht1 Label |prefetcht2 Label
PREFETCH
Usage: PREFETCH src Modifies flags: None
Loads a processor cache line into the data cache. The address of this line is specified by the mem8 value.
Prefetch Data Into Caches
PREFETCH mem8 ; 0F 0D /0 [PENT,3DNOW]
PREFETCHW mem8 ; 0F 0D /1 [PENT,3DNOW]
PREFETCH and PREFETCHW fetch the line of data from memory that contains the specified byte. PREFETCHW performs differently on the Athlon to earlier processors.
For the AMD processor, the line size is 32 bytes. In all future processors, the size of the line that is loaded by the PREFETCH instruction will be at least 32-bytes. If a cache hit occurs (the line is already in the Dcache) or a memory fault is detected, no bus cycle is initiated and the instruction is treated as a NOP. For more details, see the 3DNow! Technology Manual.
Example:
prefetch Label
POR
Usage: POR dest,src Modifies flags: None
Performs a bitwise logical OR operation on the 'src' operand and the 'dest' and stores the result in the 'dest'.
MMX Bitwise OR
POR mm1,mm2/m64 ; 0F EB /r [PENT,MMX]
POR xmm1,xmm2/m128 ; 66 0F EB /r [WILLAMETTE,SSE2]
POR performs a bitwise OR operation between its two operands (i.e. each bit of the result is 1 if and only if at least one of the corresponding bits of the two inputs was 1), and stores the result in the destination (first) operand.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register. Each bit of the result is set to 1 if either or both of the corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
EXAMPLE:
por xmm1 Label
POPF
Usage: POPF Modifies flags: all flags
Pops word/doubleword from stack into the Flags Register and then increments SP by 2 (for POPF) or 4 (for POPFD).
Pop Flags Register
POPF ; 9D [186]
POPFW ; o16 9D [186]
POPFD ; o32 9D [386]
POPFW pops a word from the stack and stores it in the bottom 16 bits of the flags register (or the whole flags register, on processors below a 386).
POPFD pops a doubleword and stores it in the entire flags register.
POPF is an alias mnemonic for either POPFD, under 32 Bits mode.
See also PUSHF ().
Example:
popf
POPA
Usage: POPA Modifies flags: None
Pops the top 8 words off the stack into the 8 general purpose 16/32 bit registers. Registers are popped in the following order: (E)DI, (E)SI, (E)BP, (E)SP, (E)DX, (E)CX and (E)AX. The (E)SP value popped from the stack is actually discarded.
Pop All General-Purpose Registers
POPA ; 61 [186]
POPAW ; o16 61 [186]
POPAD ; o32 61 [386]
POPAW pops a word from the stack into each of, successively, DI, SI, BP, nothing (it discards a word from the stack which was a placeholder for SP), BX, DX, CX and AX. It is intended to reverse the operation of PUSHAW (see ), but it ignores the value for SP that was pushed on the stack by PUSHAW.
POPAD pops twice as much data, and places the results in EDI, ESI, EBP, nothing (placeholder for ESP), EBX, EDX, ECX and EAX. It reverses the operation of PUSHAD.
POPA is an alias mnemonic for either POPAD, under 32 bit mode.
Note that the registers are popped in reverse order of their numeric values in opcodes (see rv).
Example:
pushad
call Goofy ; he uses all the registers
popad
POPA
Usage: POPA Modifies flags: None
Pops the top 8 words off the stack into the 8 general purpose 16/32 bit registers. Registers are popped in the following order: (E)DI, (E)SI, (E)BP, (E)SP, (E)DX, (E)CX and (E)AX. The (E)SP value popped from the stack is actually discarded.
Pop All General-Purpose Registers
POPA ; 61 [186]
POPAW ; o16 61 [186]
POPAD ; o32 61 [386]
POPAW pops a word from the stack into each of, successively, DI, SI, BP, nothing (it discards a word from the stack which was a placeholder for SP), BX, DX, CX and AX. It is intended to reverse the operation of PUSHAW (see ), but it ignores the value for SP that was pushed on the stack by PUSHAW.
POPAD pops twice as much data, and places the results in EDI, ESI, EBP, nothing (placeholder for ESP), EBX, EDX, ECX and EAX. It reverses the operation of PUSHAD.
POPA is an alias mnemonic for either POPAD, under 32 bit mode.
Note that the registers are popped in reverse order of their numeric values in opcodes (see rv).
Example:
pushad
call Goofy ; he uses all the registers
popad
POPA
Usage: POPA Modifies flags: None
Pops the top 8 words off the stack into the 8 general purpose 16/32 bit registers. Registers are popped in the following order: (E)DI, (E)SI, (E)BP, (E)SP, (E)DX, (E)CX and (E)AX. The (E)SP value popped from the stack is actually discarded.
Pop All General-Purpose Registers
POPA ; 61 [186]
POPAW ; o16 61 [186]
POPAD ; o32 61 [386]
POPAW pops a word from the stack into each of, successively, DI, SI, BP, nothing (it discards a word from the stack which was a placeholder for SP), BX, DX, CX and AX. It is intended to reverse the operation of PUSHAW (see ), but it ignores the value for SP that was pushed on the stack by PUSHAW.
POPAD pops twice as much data, and places the results in EDI, ESI, EBP, nothing (placeholder for ESP), EBX, EDX, ECX and EAX. It reverses the operation of PUSHAD.
POPA is an alias mnemonic for either POPAD, under 32 bit mode.
Note that the registers are popped in reverse order of their numeric values in opcodes (see rv).
Example:
pushad
call Goofy ; he uses all the registers
popad
POP
Usage: POP dest Modifies flags: None
Transfers word at the current stack top ESP to the 'dest' then increments ESP by two to point to the new stack top. CS is not a valid destination.
Pop Data from Stack
POP reg16 ; o16 58+r [8086]
POP reg32 ; o32 58+r [386]
POP r/m16 ; o16 8F /0 [8086]
POP r/m32 ; o32 8F /0 [386]
POP CS ; 0F [8086,UNDOC]
POP DS ; 1F [8086]
POP ES ; 07 [8086]
POP SS ; 17 [8086]
POP FS ; 0F A1 [386]
POP GS ; 0F A9 [386]
POP loads a value from the stack (from ESP) and then increments the stack pointer.
The address-size attribute of the instruction determines whether ESP is used as the stack pointer.
The above opcode listings give two forms for general-purpose register pop instructions: for example, POP BX has the two forms B and F C3. RosAsm will always generate the shorter form when given POP BX.
POP CS is not a documented instruction, and is not supported on any processor above the 8086 (since they use Fh as an opcode prefix for instruction set extensions). However, at least some 8086 processors do support it, and so RosAsm generates it for completeness.
Example:
xor ebx ebx
mov eax 15
push eax
pop ebx ; ebx = 15