PUSHA
Usage: PUSHA Modifies flags: None
Pushes all general purpose registers onto the stack in the following order: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The value of ESP or SP is the value before the actual push of ESP or SP.
Push All General-Purpose Registers
PUSHA ; 60 [186]
PUSHAD ; o32 60 [386]
PUSHAW ; o16 60 [186]
PUSHAW pushes, in succession, AX, CX, DX, BX, SP, BP, SI and DI on the stack, decrementing the stack pointer by a total of 16.
PUSHAD pushes, in succession, EAX, ECX, EDX, EBX, ESP, EBP, ESI and EDI on the stack, decrementing the stack pointer by a total of 32.
In both cases, the value of SP or ESP pushed is its value, as it had before the instruction was executed.
PUSHA is an alias mnemonic for PUSHAD, under 32 Bits mode.
Note that the registers are pushed in order of their numeric values in opcodes (see rv).
See also POPA ().
Example:
pushad
call Goofy ;he uses all the registers
popad
PUSHA
Usage: PUSHA Modifies flags: None
Pushes all general purpose registers onto the stack in the following order: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The value of ESP or SP is the value before the actual push of ESP or SP.
Push All General-Purpose Registers
PUSHA ; 60 [186]
PUSHAD ; o32 60 [386]
PUSHAW ; o16 60 [186]
PUSHAW pushes, in succession, AX, CX, DX, BX, SP, BP, SI and DI on the stack, decrementing the stack pointer by a total of 16.
PUSHAD pushes, in succession, EAX, ECX, EDX, EBX, ESP, EBP, ESI and EDI on the stack, decrementing the stack pointer by a total of 32.
In both cases, the value of SP or ESP pushed is its value, as it had before the instruction was executed.
PUSHA is an alias mnemonic for PUSHAD, under 32 Bits mode.
Note that the registers are pushed in order of their numeric values in opcodes (see rv).
See also POPA ().
Example:
pushad
call Goofy ;he uses all the registers
popad
PUSHA
Usage: PUSHA Modifies flags: None
Pushes all general purpose registers onto the stack in the following order: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The value of ESP or SP is the value before the actual push of ESP or SP.
Push All General-Purpose Registers
PUSHA ; 60 [186]
PUSHAD ; o32 60 [386]
PUSHAW ; o16 60 [186]
PUSHAW pushes, in succession, AX, CX, DX, BX, SP, BP, SI and DI on the stack, decrementing the stack pointer by a total of 16.
PUSHAD pushes, in succession, EAX, ECX, EDX, EBX, ESP, EBP, ESI and EDI on the stack, decrementing the stack pointer by a total of 32.
In both cases, the value of SP or ESP pushed is its value, as it had before the instruction was executed.
PUSHA is an alias mnemonic for PUSHAD, under 32 Bits mode.
Note that the registers are pushed in order of their numeric values in opcodes (see rv).
See also POPA ().
Example:
pushad
call Goofy ;he uses all the registers
popad
PUSHA
Usage: PUSHA Modifies flags: None
Pushes all general purpose registers onto the stack in the following order: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The value of ESP or SP is the value before the actual push of ESP or SP.
Push All General-Purpose Registers
PUSHA ; 60 [186]
PUSHAD ; o32 60 [386]
PUSHAW ; o16 60 [186]
PUSHAW pushes, in succession, AX, CX, DX, BX, SP, BP, SI and DI on the stack, decrementing the stack pointer by a total of 16.
PUSHAD pushes, in succession, EAX, ECX, EDX, EBX, ESP, EBP, ESI and EDI on the stack, decrementing the stack pointer by a total of 32.
In both cases, the value of SP or ESP pushed is its value, as it had before the instruction was executed.
PUSHA is an alias mnemonic for PUSHAD, under 32 Bits mode.
Note that the registers are pushed in order of their numeric values in opcodes (see rv).
See also POPA ().
Example:
pushad
call Goofy ;he uses all the registers
popad
PUSH
Usage: PUSH src Modifies flags: None
Decrements ESP by the size of the operand (two or four, byte values are sign extended) and transfers the source value to the stack top.
Push Data on Stack
PUSH reg16 ; o16 50+r [8086]
PUSH reg32 ; o32 50+r [386]
PUSH r/m16 ; o16 FF /6 [8086]
PUSH r/m32 ; o32 FF /6 [386]
PUSH CS ; 0E [8086]
PUSH DS ; 1E [8086]
PUSH ES ; 06 [8086]
PUSH SS ; 16 [8086]
PUSH FS ; 0F A0 [386]
PUSH GS ; 0F A8 [386]
PUSH imm8 ; 6A ib [186]
PUSH imm16 ; o16 68 iw [186]
PUSH imm32 ; o32 68 id [386]
PUSH decrements the stack pointer (ESP) by 2 or 4, and then stores the given value at ESP.
The above opcode listings give two forms for general-purpose push instructions: for example, PUSH BX has the two forms and FF F3. RosAsm will always generate the shorter form when given PUSH BX.
Unlike the undocumented and barely supported POP CS, PUSH CS is a perfectly valid and sensible instruction, supported on all processors.
The instruction PUSH SP may be used to distinguish an 8086 from later processors: on an 8086, the value of SP stored is the value it has the push instruction, whereas on later processors it is the value the push instruction.
Example:
mov eax 15
push eax
pop ebx ; ebx = 15
PUNPCKxxx
Usage: PUNPCKxxx dest,src Modifies flags: None
Unpacks and interleaves the high or low order data elements (bytes, words, doublewords, or quadwords) of the 'dest' and 'src' operand into the 'dest' operand.
Unpack and Interleave Data
PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX]
PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX]
PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX]
PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2]
PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2]
PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2]
PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2]
PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX]
PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX]
PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX]
PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2]
PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2]
PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2]
PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2]
PUNPCKxx all treat their operands as vectors, and produce a new vector generated by interleaving elements from the two inputs. The PUNPCKHxx instructions start by throwing away the bottom half of each input operand, and the PUNPCKLxx instructions throw away the top half.
The remaining elements, are then interleaved into the destination, alternating elements from the second (source) operand and the first (destination) operand: so the leftmost part of each element in the result always comes from the second operand, and the rightmost from the destination.
PUNPCKxBW works a byte at a time, producing word sized output elements.
PUNPCKxWD works a word at a time, producing doubleword sized output elements.
PUNPCKxDQ works a doubleword at a time, producing quadword sized output elements.
PUNPCKxQDQ works a quadword at a time, producing double quadword sized elements.
So, for example, for MMX operands, if the first operand held x7A6A5A4A3A2A1A0A and the second held x7B6B5B4B3B2B1B0B, then:
PUNPCKHBW Unpack high-order bytes would return x7B7A6B6A5B5A4B4A.
PUNPCKHWD Unpack high-order words would return x7B6B7A6A5B4B5A4A.
PUNPCKHDQ Unpack high-order doublewords would return x7B6B5B4B7A6A5A4A.
PUNPCKLBW Unpack low-order bytes would return x3B3A2B2A1B1A0B0A.
PUNPCKLWD Unpack low-order words would return x3B2B3A2A1B0B1A0A.
PUNPCKLDQ Unpack low-order doublewords would return x3B2B1B0B3A2A1A0A.
EXAMPLE:
punpckhbw xmm1 xmm2
PUNPCKxxx: Unpack and Interleave Data
PUNPCKHBW mm1,mm2/m64 ; 0F 68 /r [PENT,MMX]
PUNPCKHWD mm1,mm2/m64 ; 0F 69 /r [PENT,MMX]
PUNPCKHDQ mm1,mm2/m64 ; 0F 6A /r [PENT,MMX]
PUNPCKHBW xmm1,xmm2/m128 ; 66 0F 68 /r [WILLAMETTE,SSE2]
PUNPCKHWD xmm1,xmm2/m128 ; 66 0F 69 /r [WILLAMETTE,SSE2]
PUNPCKHDQ xmm1,xmm2/m128 ; 66 0F 6A /r [WILLAMETTE,SSE2]
PUNPCKHQDQ xmm1,xmm2/m128 ; 66 0F 6D /r [WILLAMETTE,SSE2]
PUNPCKLBW mm1,mm2/m32 ; 0F 60 /r [PENT,MMX]
PUNPCKLWD mm1,mm2/m32 ; 0F 61 /r [PENT,MMX]
PUNPCKLDQ mm1,mm2/m32 ; 0F 62 /r [PENT,MMX]
PUNPCKLBW xmm1,xmm2/m128 ; 66 0F 60 /r [WILLAMETTE,SSE2]
PUNPCKLWD xmm1,xmm2/m128 ; 66 0F 61 /r [WILLAMETTE,SSE2]
PUNPCKLDQ xmm1,xmm2/m128 ; 66 0F 62 /r [WILLAMETTE,SSE2]
PUNPCKLQDQ xmm1,xmm2/m128 ; 66 0F 6C /r [WILLAMETTE,SSE2]
PUNPCKxx all treat their operands as vectors, and produce a new vector generated by interleaving elements from the two inputs. The PUNPCKHxx instructions start by throwing away the bottom half of
each input operand, and the PUNPCKLxx instructions throw away the top half.
The remaining elements, are then interleaved into the destination, alternating elements from the second (source) operand and the first (destination) operand: so the leftmost part of each element in the
result always comes from the second operand, and the rightmost from the destination.
PUNPCKxBW works a byte at a time, producing word sized output
elements.
PUNPCKxWD works a word at a time, producing doubleword sized
output elements.
PUNPCKxDQ works a doubleword at a time, producing quadword sized
output elements.
PUNPCKxQDQ works a quadword at a time, producing double quadword
sized output elements.
So, for example, for MMX operands, if the first operand held x7A6A5A4A3A2A1A0A and the second held x7B6B5B4B3B2B1B0B, then:
PUNPCKHBW would return x7B7A6B6A5B5A4B4A.
PUNPCKHWD would return x7B6B7A6A5B4B5A4A.
PUNPCKHDQ would return x7B6B5B4B7A6A5A4A.
PUNPCKLBW would return x3B3A2B2A1B1A0B0A.
PUNPCKLWD would return x3B2B3A2A1B0B1A0A.
PUNPCKLDQ would return x3B2B1B0B3A2A1A0A.
PSWAPD PSWAPW
Usage: PSWAPD dest,src Modifies flags: None
Reverses the upper and lower doublewords of the source operand.
Swap Packed Data
PSWAPD mm1,mm2/m64 ; 0F 0F /r BB [PENT,3DNOW]
PSWAPD swaps the packed doublewords in the source operand, and stores the result in the destination operand.
In the K6-2 and K6-III processors, this opcode uses the mnemonic PSWAPW, and it swaps the order of words when copying from the source to the destination.
The operation in the K6-2 and K6-III processors is:
dst[0-15] = src[48-63];
dst[16-31] = src[32-47];
dst[32-47] = src[16-31];
dst[48-63] = src[0-15].
The operation in the K6-x+, ATHLON and later processors is:
dst[0-31] = src[32-63];
dst[32-63] = src[0-31].
EXAMPLE:
pswapd mm1 mm2
PSUBxx
Usage: PSUBxx dest,src Modifies flags: None
Performs an SIMD subtract of the packed signed integers of the 'src' from the packed signed integers of the 'dest' and stores the packed integer results in the 'dest' operand. Over-flow is handled with signed saturation. These instructions can operate on either 64-bit or 128-bit operands.
Subtract Packed Integers With Saturation
PSUBSB mm1,mm2/m64 ; 0F E8 /r [PENT,MMX]
PSUBSW mm1,mm2/m64 ; 0F E9 /r [PENT,MMX]
PSUBSB xmm1,xmm2/m128 ; 66 0F E8 /r [WILLAMETTE,SSE2]
PSUBSW xmm1,xmm2/m128 ; 66 0F E9 /r [WILLAMETTE,SSE2]
PSUBUSB mm1,mm2/m64 ; 0F D8 /r [PENT,MMX]
PSUBUSW mm1,mm2/m64 ; 0F D9 /r [PENT,MMX]
PSUBUSB xmm1,xmm2/m128 ; 66 0F D8 /r [WILLAMETTE,SSE2]
PSUBUSW xmm1,xmm2/m128 ; 66 0F D9 /r [WILLAMETTE,SSE2]
PSUBx and PSUBUxx subtracts packed integers in the source operand from those in the destination operand, and use saturation for results that are outide the range supported by the destination operand.
PSUBSB operates on signed bytes. PSUBSW operates on signed words.
PSUBUSB operates on unsigned bytes. PSUBUSW operates on unsigned words.
EXAMPLE:
psubsb xmm1 Label|psubsw xmm1 Label|psubusb xmm1 Label|psubusw xmm1 Label
PSUBx
Usage: PSUBx dest,src Modifies flags: None
Performs an SIMD subtract of the packed integers of the 'src (second operand) from the packed integers of the 'dest' (first operand), and stores the packed integer results in the 'dest' operand.
Subtract Packed Integers
PSUBB mm1,mm2/m64 ; 0F F8 /r [PENT,MMX]
PSUBW mm1,mm2/m64 ; 0F F9 /r [PENT,MMX]
PSUBD mm1,mm2/m64 ; 0F FA /r [PENT,MMX]
PSUBQ mm1,mm2/m64 ; 0F FB /r [WILLAMETTE,SSE2]
PSUBB xmm1,xmm2/m128 ; 66 0F F8 /r [WILLAMETTE,SSE2]
PSUBW xmm1,xmm2/m128 ; 66 0F F9 /r [WILLAMETTE,SSE2]
PSUBD xmm1,xmm2/m128 ; 66 0F FA /r [WILLAMETTE,SSE2]
PSUBQ xmm1,xmm2/m128 ; 66 0F FB /r [WILLAMETTE,SSE2]
PSUBx subtracts packed integers in the source operand from those in the destination operand. It doesn't differentiate between signed and unsigned integers, and doesn't set any of the flags.
PSUBB operates on byte sized elements. PSUBW operates on word sized elements.
PSUBD operates on doubleword sized. PSUBQ operates on quadword sized.
These instructions can operate on either 64-bit or 128-bit operands. When operating on 64-bit operands, the 'dest' operand must be an MMX technology register and the 'src' operand can be either an MMX technology register or a 64-bit memory location. When operating on 128-bit operands, the 'dest' operand must be an XMM register and the 'src' operand can be either an XMM register or a 128-bit memory location.
EXAMPLE:
psubb xmm1 Label | psubw xmm1 Label | psubd xmm1 Label| psubq xmm1 Label