PAVGW
Usage: PAVGB dest,src Modifies flags: None
Performs an SIMD average of the packed unsigned integers from the 'src' and the 'dest' , and stores the results in the 'dest' operand. For each corresponding pair of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary sum, and that result is shifted right one bit position.
Average Packed Integers
PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX]
PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM]
PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2]
PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2]
PAVGB and PAVGW add the unsigned data elements of the source operand to the unsigned data elements of the destination register, then adds 1 to the temporary results. The results of the add are then each independently right-shifted by one bit position. The high order bits of each element are filled with the carry bits of the corresponding sum.
PAVGB operates on packed unsigned bytes, and
PAVGW operates on packed unsigned words.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register.
EXAMPLE:
pavgw xmm1 Label
PAVGUSB
Usage: PAVGUSB dest,src Modifies flags: None
The PAVGUSB instruction produces the rounded averages of the eight unsigned 8-bit integer values in the 'src' operand (an MMX register or a 64-bit memory location) and the eight corresponding unsigned 8-bit integer values in the 'dest' operand (an MMX register). It does so by adding the 'src' and 'dest' byte values and then adding a 001h to the 9-bit intermediate value. The intermediate value is then divided by 2 (shifted right one place) and the eight unsigned 8-bit results are stored in the MMX register specified as the destination operand.
Average of unsigned packed 8-bit values
PAVGUSB mm1,mm2/m64 ; 0F 0F /r BF [PENT,3DNOW]
PAVGUSB adds the unsigned data elements of the source operand to the unsigned data elements of the destination register, then adds 1 to the temporary results. The results of the add are then each independently right-shifted by one bit position. The high order bits of each element are filled with the carry bits of the corresponding sum.
This instruction performs exactly the same operations as the PAVGB MMX instruction.
Example:
pavgusb mm1 mm2
PAVGB
Usage: PAVGB dest,src Modifies flags: None
Performs an SIMD average of the packed unsigned integers from the 'src' (second operand) and the 'dest' (first operand), and stores the results in the 'dest' operand. For each corresponding pair of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary sum, and that result is shifted right one bit position.
Average Packed Integers
PAVGB mm1,mm2/m64 ; 0F E0 /r [KATMAI,MMX]
PAVGW mm1,mm2/m64 ; 0F E3 /r [KATMAI,MMX,SM]
PAVGB xmm1,xmm2/m128 ; 66 0F E0 /r [WILLAMETTE,SSE2]
PAVGW xmm1,xmm2/m128 ; 66 0F E3 /r [WILLAMETTE,SSE2]
PAVGB and PAVGW add the unsigned data elements of the source operand to the unsigned data elements of the destination register, then adds 1 to the temporary results. The results of the add are then each independently right-shifted by one bit position. The high order bits of each element are filled with the carry bits of the corresponding sum.
PAVGB operates on packed unsigned bytes, and
PAVGW operates on packed unsigned words.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register.
EXAMPLE:
pavgb xmm1 Label
PAUSE
Usage: PAUSE Modifies flags: None
Improves the performance of spin-wait loops. When executing a 'spin-wait loop,' a Pentium 4 or Intel Xeon processor suffers a severe performance penalty when exiting the loop because it detects a possible memory order violation. Spin Loop Hint
PAUSE ; F3 90 [WILLAMETTE,SSE2]
PAUSE provides a hint to the processor that the following code is a spin loop. This improves processor performance by bypassing possible memory order violations. On older processors, this instruction operates as a NOP.
The processor uses this hint to avoid the memory order violation in most situations, which greatly improves processor performance. For this reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.
EXAMPLE:
pause
PANDN
Usage: PANDN dest,src Modifies flags: None
Performs a bitwise logical NOT of the 'dest' then performs a bitwise logical AND of the 'src' and the inverted 'dest' operand. The result is stored in the 'dest' operand.
MMX Bitwise AND and AND-NOT
PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX]
PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX]
PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2]
PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2]
PAND performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the destination (first) operand.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register.
PANDN performs the same operation, but performs a one's complement operation on the destination (first) operand first.
EXAMPLE:
pandn xmm1 Label
PAND
Usage: PAND dest,src Modifies flags: None
Performs a bitwise logical AND operation on the 'src' and the 'dest' and stores the result in the 'dest' operand.
MMX Bitwise AND and AND-NOT
PAND mm1,mm2/m64 ; 0F DB /r [PENT,MMX]
PANDN mm1,mm2/m64 ; 0F DF /r [PENT,MMX]
PAND xmm1,xmm2/m128 ; 66 0F DB /r [WILLAMETTE,SSE2]
PANDN xmm1,xmm2/m128 ; 66 0F DF /r [WILLAMETTE,SSE2]
PAND performs a bitwise AND operation between its two operands (i.e. each bit of the result is 1 if and only if the corresponding bits of the two inputs were both 1), and stores the result in the destination (first) operand.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register.
PANDN performs the same operation, but performs a one's complement operation on the destination (first) operand first.
EXAMPLE:
pand xmm1 Label
PADDW
Usage: PADDW dest,src Modifies flags: None
Performs an SIMD add of the packed integers from the 'src' and the 'dest' , and stores the packed integer results in the 'dest' operand.
Add Packed Integers
PADDB mm1,mm2/m64 ; 0F FC /r [PENT,MMX]
PADDW mm1,mm2/m64 ; 0F FD /r [PENT,MMX]
PADDD mm1,mm2/m64 ; 0F FE /r [PENT,MMX]
PADDB xmm1,xmm2/m128 ; 66 0F FC /r [WILLAMETTE,SSE2]
PADDW xmm1,xmm2/m128 ; 66 0F FD /r [WILLAMETTE,SSE2]
PADDD xmm1,xmm2/m128 ; 66 0F FE /r [WILLAMETTE,SSE2]
PADDx performs packed addition of the two operands, storing the result in the destination (first) operand.
PADDB treats the operands as packed bytes, and adds each byte individually;
PADDW treats the operands as packed words;
PADDD treats its operands as packed doublewords.
When an individual result is too large to fit in its destination, it is wrapped around and the low bits are stored, with the carry bit discarded.
EXAMPLE:
paddw xmm1 Label
PADDUSW
Usage: PADDUSW dest,src Modifies flags: None
Performs an SIMD add of the packed unsigned integers from the 'src' and the 'dest' , and stores the packed integer results in the 'dest' operand. These instructions can operate on either 64-bit or 128-bit operands.
Add Packed Unsigned Integers With Saturation
PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX]
PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX]
PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2]
PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2]
PADDUSx performs packed addition of the two operands, storing the result in the destination (first) operand. PADDUSB treats the operands as packed bytes, and adds each byte individually; and PADDUSW treats the operands as packed words.
When an individual result is too large to fit in its destination, a saturated value is stored. The resulting value is the maximum value that will fit in the available space.
EXAMPLE:
paddusw xmm1 Label
PADDUSB
Usage: PADDUSB dest,src Modifies flags: None
Performs an SIMD add of the packed unsigned integers from the 'src' and the 'dest', and stores the packed integer results in the 'dest' operand. These instructions can operate on either 64-bit or 128-bit operands.
Add Packed Unsigned Integers With Saturation
PADDUSB mm1,mm2/m64 ; 0F DC /r [PENT,MMX]
PADDUSW mm1,mm2/m64 ; 0F DD /r [PENT,MMX]
PADDUSB xmm1,xmm2/m128 ; 66 0F DC /r [WILLAMETTE,SSE2]
PADDUSW xmm1,xmm2/m128 ; 66 0F DD /r [WILLAMETTE,SSE2]
PADDUSx performs packed addition of the two operands, storing the result in the destination (first) operand. PADDUSB treats the operands as packed bytes, and adds each byte individually; and PADDUSW treats the operands as packed words.
When an individual result is too large to fit in its destination, a saturated value is stored. The resulting value is the maximum value that will fit in the available space.
EXAMPLE:
paddusb xmm1 Label
PADDSW
Usage: PADDSW dest,src Modifies flags: None
Performs an SIMD add of the packed signed integers from the 'src' and the 'dest', and stores the packed integer results in the 'dest' operand. These instructions can operate on either 64-bit or 128-bit operands.
Add Packed Signed Integers With Saturation
PADDSB mm1,mm2/m64 ; 0F EC /r [PENT,MMX]
PADDSW mm1,mm2/m64 ; 0F ED /r [PENT,MMX]
PADDSB xmm1,xmm2/m128 ; 66 0F EC /r [WILLAMETTE,SSE2]
PADDSW xmm1,xmm2/m128 ; 66 0F ED /r [WILLAMETTE,SSE2]
PADDSx performs packed addition of the two operands, storing the result in the destination (first) operand. PADDSB treats the operands as packed bytes, and adds each byte individually; and PADDSW treats the operands as packed words.
When an individual result is too large to fit in its destination, a saturated value is stored. The resulting value is the value with the largest magnitude of the same sign as the result which will fit in the available space.
EXAMPLE:
paddsw xmm1 Label