RDPMC
Usage: RDPMC counter Modifies flags: None
Loads the contents of the 40-bit performance-monitoring 'counter' specified in the ECX register into registers EDX:EAX.
Read Performance-Monitoring Counters
RDPMC ; 0F 33 [P6]
RDPMC reads the processor performance-monitoring counter whose index is stored in ECX , and stores the result in EDX:EAX.
The EDX register is loaded with the high-order 8 bits of the counter and the EAX register is loaded with the low-order 32 bits.
The counter to be read is specified with an unsigned integer placed in the ECX register.
The P6 family processors and Pentium processors with MMX technology have two performance-monitoring counters (0 and 1), which are specified by placing 0000H or 0001H, respectively, in the ECX register.
The Pentium 4 and Intel Xeon processors have 18 counters (0 through 17), which are specified with 0000H through 0011H, respectively.
This instruction is available on P6 and later processors and on MMX class processors.
EXAMPLE:
mov ecx 1
rdpmc