REP
Usage: REP Instruction Modifies flags: None
Repeats a string instruction the number of times specified in the count register (E)CX or until the indicated condition of the ZF flag is no longer met.
Repeat String Operation Prefix. REPE REPNE REPZ REPNZ
REP instruction ; oF3 ... [386]
REPE instruction ; oF3 ... [386]
REPZ instruction ; oF3 ... [386]
REPNE instruction ; oF2 ... [386]
REPNZ instruction ; oF2 ... [386]
Repeats the 'Instruction' ECX times which may be: CMPSB MOVSB LODSB STOSB SCASB INSB OUTSB , and other Words and dWords forms of these Mnemonics.
The 'E' and 'Z' forms of REP are equivalent (The 'E' and 'Z' Flags are one and same), standing both for 'Equal' and 'Zeroed'. The instruction is repeated ECX times, unless the Flag condition is not matched. Zero flag inicates equal or zero.
The 'NE' and 'NZ' forms of REP are also equivalent. 'N' stands for 'Not' and the instruction is repeated ECX times, unless the negative condition of the Flag is not matched. Zero flag inicates not equal or not zero.
The behavior of the REP prefix is undefined when used with non-string instructions
Example:
mov edi SourcePointer
mov ecx MAX_POSSIBLE_LENGTH
mov al 'A'
repne scasb | je Found
; Not found = repeat
Found:
.
RDTSC
Usage: RDTSC Modifies flags: None
Read time-stamp counter into EDX:EAX.
Read Time-Stamp Counter
RDTSC ; 0F 31 [PENT]
RDTSC . Loads the current value of the processor's time-stamp counter into the EDX:EAX registers. The time-stamp counter is contained in a 64-bit MSR. The high-order 32 bits of the MSR are loaded into the EDX register, and the low-order 32 bits are loaded into the EAX register.
The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset.
EXAMPLE:
rdtsc
RDPMC
Usage: RDPMC counter Modifies flags: None
Loads the contents of the 40-bit performance-monitoring 'counter' specified in the ECX register into registers EDX:EAX.
Read Performance-Monitoring Counters
RDPMC ; 0F 33 [P6]
RDPMC reads the processor performance-monitoring counter whose index is stored in ECX , and stores the result in EDX:EAX.
The EDX register is loaded with the high-order 8 bits of the counter and the EAX register is loaded with the low-order 32 bits.
The counter to be read is specified with an unsigned integer placed in the ECX register.
The P6 family processors and Pentium processors with MMX technology have two performance-monitoring counters (0 and 1), which are specified by placing 0000H or 0001H, respectively, in the ECX register.
The Pentium 4 and Intel Xeon processors have 18 counters (0 through 17), which are specified with 0000H through 0011H, respectively.
This instruction is available on P6 and later processors and on MMX class processors.
EXAMPLE:
mov ecx 1
rdpmc
RDMSR
Usage: RDMSR Modifies flags: None
Loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The input value loaded into the ECX register is the address of the MSR to be read.
Read Model-Specific Registers
RDMSR ; 0F 32 [PENT,PRIV]
RDMSR reads the processor Model-Specific Register (MSR) whose index is stored in ECX, and stores the result in EDX:EAX. See also WRMSR.
The MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor results in an invalid opcode exception #UD.
The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. If fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.
Example:
mov ecx MsrAddr
rdmsr ; edx = ValueHi , eax = ValueLo
RCR
Usage: RCR dest,count Modifies flags: CF OF
Rotates the bits in the destination to the right 'count' times with all data pushed out the right side re-entering on the left. The Carry Flag holds the last bit rotated out.
Bitwise Rotate through Carry Bit
RCL r/m8,1 ; D0 /2 [8086]
RCL r/m8,CL ; D2 /2 [8086]
RCL r/m8,imm8 ; C0 /2 ib [186]
RCL r/m16,1 ; o16 D1 /2 [8086]
RCL r/m16,CL ; o16 D3 /2 [8086]
RCL r/m16,imm8 ; o16 C1 /2 ib [186]
RCL r/m32,1 ; o32 D1 /2 [386]
RCL r/m32,CL ; o32 D3 /2 [386]
RCL r/m32,imm8 ; o32 C1 /2 ib [386]
RCR r/m8,1 ; D0 /3 [8086]
RCR r/m8,CL ; D2 /3 [8086]
RCR r/m8,imm8 ; C0 /3 ib [186]
RCR r/m16,1 ; o16 D1 /3 [8086]
RCR r/m16,CL ; o16 D3 /3 [8086]
RCR r/m16,imm8 ; o16 C1 /3 ib [186]
RCR r/m32,1 ; o32 D1 /3 [386]
RCR r/m32,CL ; o32 D3 /3 [386]
RCR r/m32,imm8 ; o32 C1 /3 ib [386]
RCL and RCR perform a 9-bit, 17-bit or 33-bit bitwise rotation operation, involving the given source/destination (first) operand and the carry bit. Thus, for example, in the operation RCL AL,1, a 9-bit rotation is performed in which AL is shifted left by 1, the top bit of AL moves into the carry flag, and the original value of the carry flag is placed in the low bit of AL.
The number of bits to rotate by is given by the second operand. Only the bottom five bits of the rotation count are considered by processors above the 8086.
Example:
mov eax 144 ; eax = 90h
rcr eax 1 ; eax = 48h > 72d
RCPSS
Usage: RCPSS dest,src Modifies flags: None
Computes an approximate reciprocal of the low single-precision floating-point value in the 'src' and stores the single-precision floating-point result in the 'dest' operand.
Scalar Single-Precision FP Reciprocal
RCPSS xmm1,xmm2/m128 ; F3 0F 53 /r [KATMAI,SSE]
RCPSS returns an approximation of the reciprocal of the lower single-precision FP value from xmm2/m32; the upper three fields are passed through from xmm1. The maximum error for this approximation is: |Error| <= 1.5 x 2^-12.
The 'src' operand can be an XMM register or a 32-bit memory location. The 'dest' operand is an XMM register. The three high-order doublewords of the 'dest' operand remain unchanged.
EXAMPLE:
rcpss xmm1 xmm2
RCPPS
Usage: RCPPS dest,src Modifies flags: None
Performs an SIMD computation of the approximate reciprocals of the four packed single-precision floating-point values in the 'src' then stores the packed single-precision floating-point result in the 'dest' operand.
Packed Single-Precision FP Reciprocal
RCPPS xmm1,xmm2/m128 ; 0F 53 /r [KATMAI,SSE]
RCPPS returns an approximation of the reciprocal of the packed single-precision FP values from xmm2/m128. The maximum error for this approximation is: |Error| <= 1.5 x 2^-12
The 'src' operand can be an XMM register or a 128-bit memory location. The 'dest' operand is an XMM register.
EXAMPLE:
rcpps xmm1 xmm2
RCL
Usage: RCL dest,count Modifies flags: CF OF
Rotates the bits in the destination to the left 'count' times with all data pushed out the left side re-entering on the right. The Carry Flag holds the last bit rotated out.
Bitwise Rotate through Carry Bit
RCL r/m8,1 ; D0 /2 [8086]
RCL r/m8,CL ; D2 /2 [8086]
RCL r/m8,imm8 ; C0 /2 ib [186]
RCL r/m16,1 ; o16 D1 /2 [8086]
RCL r/m16,CL ; o16 D3 /2 [8086]
RCL r/m16,imm8 ; o16 C1 /2 ib [186]
RCL r/m32,1 ; o32 D1 /2 [386]
RCL r/m32,CL ; o32 D3 /2 [386]
RCL r/m32,imm8 ; o32 C1 /2 ib [386]
RCR r/m8,1 ; D0 /3 [8086]
RCR r/m8,CL ; D2 /3 [8086]
RCR r/m8,imm8 ; C0 /3 ib [186]
RCR r/m16,1 ; o16 D1 /3 [8086]
RCR r/m16,CL ; o16 D3 /3 [8086]
RCR r/m16,imm8 ; o16 C1 /3 ib [186]
RCR r/m32,1 ; o32 D1 /3 [386]
RCR r/m32,CL ; o32 D3 /3 [386]
RCR r/m32,imm8 ; o32 C1 /3 ib [386]
RCL and RCR perform a 9-bit, 17-bit or 33-bit bitwise rotation operation, involving the given source/destination (first) operand and the carry bit. Thus, for example, in the operation RCL AL,1, a 9-bit rotation is performed in which AL is shifted left by 1, the top bit of AL moves into the carry flag, and the original value of the carry flag is placed in the low bit of AL.
The number of bits to rotate by is given by the second operand. Only the bottom five bits of the rotation count are considered by processors above the 8086.
Example:
mov eax 144
rcl eax 1 ; eax = 120h > 288d
mov eax 144
rcl eax 2 ; eax = 240h > 576d
PXOR
Usage: PXOR dest,src,order Modifies flags: CF OF PF SF ZF (AF undefined)
Performs a logical Exclusive-OR (XOR) operation on the 'src' and the 'dest' and stores the result in the 'dest'.
MMX Bitwise XOR
PXOR mm1,mm2/m64 ; 0F EF /r [PENT,MMX]
PXOR xmm1,xmm2/m128 ; 66 0F EF /r [WILLAMETTE,SSE2]
PXOR performs a bitwise XOR operation between its two operands (i.e. each bit of the result is 1 if and only if exactly one of the corresponding bits of the two inputs was 1), and stores the result in the destination (first) operand.
The 'src' operand can be an MMX technology register or a 64-bit memory location or it can be an XMM register or a 128-bit memory location. The 'dest' operand can be an MMX technology register or an XMM register. Each bit of the result is 1 if the corresponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.
EXAMPLE:
pxor xmm1 xmm2
PUSHF
Usage: PUSHF Modifies flags: None
Transfers the Flags Register onto the stack. PUSHF saves a 16 bit value while PUSHFD saves a 32 bit value.
Push Flags Register
PUSHF ; 9C [186]
PUSHFD ; o32 9C [386]
PUSHFW ; o16 9C [186]
PUSHFW pushes a word from the stack and stores it in the bottom 16 bits of the flags register (or the whole flags register, on processors below a 386).
PUSHFD pushes a doubleword and stores it in the entire flags register.
PUSHF is an alias mnemonic for PUSHFD, under 32 Bits mode.
See also POPF ().
Example:
pushf