MINPS
Usage: MINPS dest,src Modifies flags: None
Performs an SIMD compare of the packed single-precision floating-point values in the 'dest' and the 'src', and returns the minimum value for each pair of values to the 'dest' operand.
Return Packed Single-Precision FP Minimum
MINPS xmm1,xmm2/m128 ; 0F 5D /r [KATMAI,SSE]
MINPS performs a SIMD compare of the packed single-precision FP numbers from xmm1 and xmm2/mem, and stores the minimum values of each pair of values in xmm1. If the values being compared are both zeroes, source2 (xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned).
The 'src' operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
EXAMPLE:
minps xmm1 Label
MINPD
Usage: MINPD dest,src Modifies flags: None
Performs an SIMD compare of the packed double-precision floating-point values in the 'dest' and the 'src' and returns the minimum value for each pair of values to the 'dest' operand.
Return Packed Double-Precision FP Minimum
MINPD xmm1,xmm2/m128 ; 66 0F 5D /r [WILLAMETTE,SSE2]
MINPD performs a SIMD compare of the packed double-precision FP numbers from xmm1 and xmm2/mem, and stores the minimum values of each pair of values in xmm1. If the values being compared are both zeroes, source2 (xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned).
The 'src' operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
EXAMPLE:
minpd xmm1 Label
MFENCE
Usage: MFENCE Modifies flags: None
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction.
Memory Fence
MFENCE ; 0F AE /6 [WILLAMETTE,SSE2]
MFENCE performs a serializing operation on all loads from memory and writes to memory that were issued before the MFENCE instruction. This guarantees that all memory reads and writes before the MFENCE instruction are completed before any reads and writes after the MFENCE instruction.
MFENCE is ordered respective to other MFENCE instructions, LFENCE, SFENCE, any memory read and any other serialising instruction (such as CPUID).
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store ordering between routines that produce weakly-ordered results and routines that consume that data.
MFENCE uses the following ModRM encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 110B
R/M (2:0) = 000B
All other ModRM encodings are defined to be reserved, and use of these encodings risks incompatibility with future processors.
See also LFENCE and SFENCE.
EXAMPLE:
mfence
MAXSS
Usage: MAXSS dest,src Modifies flags: None
Compares the low single-precision floating-point values in the 'dest' and the 'src', and returns the maximum value to the low doubleword of the 'dest' operand.
Return Scalar Single-Precision FP Maximum
MAXSS xmm1,xmm2/m32 ; F3 0F 5F /r [KATMAI,SSE]
MAXSS compares the low-order single-precision FP numbers from xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the values being compared are both zeroes, source2 (xmm2/m32) would be returned. If source2 (xmm2/m32) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned). The high three doublewords of the destination are left unchanged.
The 'src' operand can be an XMM register or a 32-bit memory location. The 'dest' operand is an XMM register. When the 'src' operand is a memory operand, only 32 bits are accessed.
EXAMPLE:
maxss mm1 Label
MAXSD
Usage: MAXSD dest,src Modifies flags: None
Compares the low double-precision floating-point values in the 'dest' and the 'src' and returns the maximum value to the low quadword of the 'dest' operand.
Return Scalar Double-Precision FP Maximum
MAXSD xmm1,xmm2/m64 ; F2 0F 5F /r [WILLAMETTE,SSE2]
MAXSD compares the low-order double-precision FP numbers from xmm1 and xmm2/mem, and stores the maximum value in xmm1. If the values being compared are both zeroes, source2 (xmm2/m64) would be returned. If source2 (xmm2/m64) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned). The high quadword of the destination is left unchanged.
The 'src' operand can be an XMM register or a 64-bit memory location. The 'dest' operand is an XMM register. When the 'src' operand is a memory operand, only 64 bits are accessed. The high quadword of the 'dest' operand remains unchanged.
EXAMPLE:
maxsd xmm1 Label
MAXPS
Usage: MAXPS dest,src Modifies flags: None
Performs an SIMD compare of the packed single-precision floating-point values in the 'dest' and the 'src' , and returns the maximum value for each pair of values to the 'dest' operand.
Return Packed Single-Precision FP Maximum
MAXPS xmm1,xmm2/m128 ; 0F 5F /r [KATMAI,SSE]
MAXPS performs a SIMD compare of the packed single-precision FP numbers from xmm1 and xmm2/mem, and stores the maximum values of each pair of values in xmm1. If the values being compared are both zeroes, source2 (xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned).
The 'src' operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
EXAMPLE:
maxps xmm1 xmm2
MAXPD
Usage: MAXPD dest,src Modifies flags: None
Performs an SIMD compare of the packed double-precision floating-point values in the 'dest' and the 'src' and returns the maximum value for each pair of values to the 'dest' operand.
Return Packed Double-Precision FP Maximum
MAXPD xmm1,xmm2/m128 ; 66 0F 5F /r [WILLAMETTE,SSE2]
MAXPD performs a SIMD compare of the packed double-precision FP numbers from xmm1 and xmm2/mem, and stores the maximum values of each pair of values in xmm1. If the values being compared are both zeroes, source2 (xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN is not returned).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.
EXAMPLE:
maxpd mm1 mm2
MASKMOVQ
Usage: MASKMOVQ src,mask Modifies flags: None
Stores selected bytes from the 'src' into a 64-bit memory location. The 'mask' selects which bytes from the 'src' operand are written to memory.
Byte Mask Write
MASKMOVQ mm1,mm2 ; 0F F7 /r [KATMAI,MMX]
MASKMOVQ stores data from mm1 to the location specified by ES:EDI. The size of the store depends on the address-size attribute. The most significant bit in each byte of the mask register mm2 is used to selectively write the data (0 = no write, 1 = write) on a per-byte basis.
The 'src' and 'mask' operands are MMX technology registers. The location of the first byte of the memory location is specified by DI/EDI and DS registers. (The size of the store address depends on the address-size attribute.)
EXAMPLE:
maskmovq mm1 mm2
MASKMOVDQU
Usage: MASKMOVDQU src,mask Modifies flags:
Stores selected bytes from the 'src' into an 128-bit memory location. The 'mask' operand selects which bytes from the 'src' operand are written to memory.
Byte Mask Write
MASKMOVDQU xmm1,xmm2 ; 66 0F F7 /r [WILLAMETTE,SSE2]
MASKMOVDQU stores data from xmm1 to the location specified by EDI. The size of the store depends on the address-size attribute. The most significant bit in each byte of the 'mask' register xmm2 is used to selectively write the data (0 = no write, 1 = write) on a per-byte basis.
The 'src' and 'mask' operands are XMM registers. The location of the first byte of the memory location is specified by EDI and DS registers. The memory location does not need to be aligned on a natural boundary. (The size of the store address depends on the address-size attribute.) The most significant bit in each byte of the 'mask' operand determines whether the corresponding byte in the 'src' operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.
EXAMPLE:
mov edi Label
mov mm0 1
maskmovdqu mm1 mm0
LTR
Usage: LTR src Modifies flags: None
Loads the current task register with the value specified in 'src'.
Load Task Register
LTR r/m16 ; 0F 00 /3 [286,PRIV]
LTR looks up the segment base and limit in the GDT or LDT descriptor specified by the segment selector given as its operand, and loads them into the Task Register.
Example:
ltr Label