LODSD
Usage: LODSD Modifies flags: None
Transfers string doubleword addressed by ESI (even if an operand is supplied) to the accumulator. ESI is incremented based on the size of the operand or based on the instruction used. If the Direction Flag is set ESI is decremented, if the Direction Flag is clear ESI is incremented. Use with REP prefixes.
Load from String
LODSB ; AC [8086]
LODSW ; o16 AD [8086]
LODSD ; o32 AD [386]
LODSB loads a byte from ESI into AL. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) ESI.
LODSW and LODSD work in the same way, but they load a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.
EXAMPLE:
L0: cmp ecx D$CaretLine | je L2
On ecx > D$LineNumber, ret
L1: lodsd | cmp al LF | jne L1<
inc ecx | jmp L0<
LODSB
Usage: LODSB Modifies flags: None
Transfers string byte addressed by ESI (even if an operand is supplied) to the accumulator. ESI is incremented based on the size of the operand or based on the instruction used. Use with REP prefixes.
Load from String
LODSB ; AC [8086]
LODSW ; o16 AD [8086]
LODSD ; o32 AD [386]
LODSB loads a byte from ESI into AL. It then increments or decrements (depending on the direction flag: increments if the flag is clear, decrements if it is set) ESI.
LODSW and LODSD work in the same way, but they load a word or a doubleword instead of a byte, and increment or decrement the addressing registers by 2 or 4 instead of 1.
EXAMPLE:
L0: cmp ecx D$CaretLine | je L2
On ecx > D$LineNumber, ret
L1: lodsb | cmp al LF | jne L1<
inc ecx | jmp L0<
LOCK
Usage: LOCK instruction,dest,src Modifies flags: None
This instruction is a prefix that causes the CPU assert a bus lock signal during the execution of the next instruction. Used to avoid two processors from updating the same data location. This should only be used to lock the bus prior to instructions in following list.
Lock Prefix
LOCK ; F0
LOCK asserts a LOCK# signal for the following Instructions:
ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG
The Destination Operand must be a Memory Reference.
Insures that the processor has exclusive use of any shared memory while the signal is asserted (In a multiprocessor environment).
Examples:
lock bts D$edi 1
lock add D$eax 010
lock cmpxcg8B Q$esi
LMSW
Usage: LMSW src Modifies flags: None
Loads the Machine Status Word (MSW) from data found at 'src'.
Load/Store Machine Status Word
LMSW r/m16 ; 0F 01 /6 [286,PRIV]
LMSW loads the bottom four bits of the source operand into the bottom four bits of the CR0 control register (or the Machine Status Word, on 286 processors).
See also SMSW.
Example:
lmsw Label
LLDT
Usage: LLDT src Modifies flags: None
Loads a value from an operand into the Local Descriptor Table Register (LDTR).
Load Descriptor Tables
LGDT mem ; 0F 01 /2 [286,PRIV]
LIDT mem ; 0F 01 /3 [286,PRIV]
LLDT r/m16 ; 0F 00 /2 [286,PRIV]
LGDT and LIDT both take a 6-byte memory area as an operand: they load a 32-bit linear address and a 16-bit size limit from that area (in the opposite order) into the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register). These are the only instructions which directly use addresses, rather than segment/offset pairs.
LLDT takes a segment selector as an operand. The processor looks up that selector in the GDT and stores the limit and base address given there into the LDTR (local descriptor table register).
See also SGDT, SIDT and SLDT.
Example:
lldt eax
LIDT
Usage: LIDT src Modifies flags: None
Loads a value from an operand into the Interrupt Descriptor Table (IDT) register.
Load Descriptor Tables
LGDT mem ; 0F 01 /2 [286,PRIV]
LIDT mem ; 0F 01 /3 [286,PRIV]
LLDT r/m16 ; 0F 00 /2 [286,PRIV]
LGDT and LIDT both take a 6-byte memory area as an operand: they load a 32-bit linear address and a 16-bit size limit from that area (in the opposite order) into the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register). These are the only instructions which directly use addresses, rather than segment/offset pairs.
LLDT takes a segment selector as an operand. The processor looks up that selector in the GDT and stores the limit and base address given there into the LDTR (local descriptor table register).lidt eax
See also SGDT, SIDT and SLDT.
Example:
lidt eax
LGS
Usage: LGS dest,src Modifies flags: None
Loads 32-bit pointer from memory 'src' to 'dest' register and GS. The offset is placed in the 'dest' register and the segment is placed in GS. To use this instruction the word at the lower memory address must contain the offset and the word at the higher address must contain the segment.
Load Far Pointer
LDS reg16,mem ; o16 C5 /r [8086]
LDS reg32,mem ; o32 C5 /r [386]
LES reg16,mem ; o16 C4 /r [8086]
LES reg32,mem ; o32 C4 /r [386]
LFS reg16,mem ; o16 0F B4 /r [386]
LFS reg32,mem ; o32 0F B4 /r [386]
LGS reg16,mem ; o16 0F B5 /r [386]
LGS reg32,mem ; o32 0F B5 /r [386]
LSS reg16,mem ; o16 0F B2 /r [386]
LSS reg32,mem ; o32 0F B2 /r [386]
These instructions load an entire far pointer (16 or 32 bits of offset, plus 16 bits of segment) out of memory in one go. LDS, for example, loads 16 or 32 bits from the given memory address into the given register (depending on the size of the register), then loads the 16 bits from memory into DS.
LES, LFS, LGS and LSS work in the same way but use the other segment registers.
Example:
lgs eax Label
LGDT
Usage: LGDT src Modifies flags: None
Loads a value from an operand into the Global Descriptor Table (GDT) register.
Load Descriptor Tables
LGDT mem ; 0F 01 /2 [286,PRIV]
LIDT mem ; 0F 01 /3 [286,PRIV]
LLDT r/m16 ; 0F 00 /2 [286,PRIV]
LGDT and LIDT both take a 6-byte memory area as an operand: they load a 32-bit linear address and a 16-bit size limit from that area (in the opposite order) into the GDTR (global descriptor table register) or IDTR (interrupt descriptor table register). These are the only instructions which directly use addresses, rather than segment/offset pairs.
LLDT takes a segment selector as an operand. The processor looks up that selector in the GDT and stores the limit and base address given there into the LDTR (local descriptor table register).
See also SGDT, SIDT and SLDT.
Example:
lgdt Label
LFS
Usage: LFS dest,src Modifies flags: None
Loads 32-bit pointer from memory 'src' to 'dest' register and FS. The offset is placed in the 'dest' register and the segment is placed in FS. To use this instruction the word at the lower memory address must contain the offset and the word at the higher address must contain the segment.
Load Far Pointer
LDS reg16,mem ; o16 C5 /r [8086]
LDS reg32,mem ; o32 C5 /r [386]
LES reg16,mem ; o16 C4 /r [8086]
LES reg32,mem ; o32 C4 /r [386]
LFS reg16,mem ; o16 0F B4 /r [386]
LFS reg32,mem ; o32 0F B4 /r [386]
LGS reg16,mem ; o16 0F B5 /r [386]
LGS reg32,mem ; o32 0F B5 /r [386]
LSS reg16,mem ; o16 0F B2 /r [386]
LSS reg32,mem ; o32 0F B2 /r [386]
These instructions load an entire far pointer (16 or 32 bits of offset, plus 16 bits of segment) out of memory in one go. LDS, for example, loads 16 or 32 bits from the given memory address into the given register (depending on the size of the register), then loads the 16 bits from memory into DS. LES, LFS, LGS and LSS work in the same way but use the other segment registers.
Example:
lfs eax Label
LFENCE
Usage: LFENCE Modifies Flags: None
Serializes load operations.
Load Fence
LFENCE ; 0F AE /5 [WILLAMETTE,SSE2]
LFENCE performs a serializing operation on all loads from memory that were issued before the LFENCE instruction. This guarantees that all memory reads before the LFENCE instruction are visible before any reads after the LFENCE instruction.
LFENCE is ordered respective to other LFENCE instruction, MFENCE, any memory read and any other serializing instruction (such as CPUID).
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE instruction provides a performance-efficient way of ensuring load ordering between routines that produce weakly-ordered results and routines that consume that data.
LFENCE uses the following ModRM encoding:
Mod (7:6) = 00_11_..._...
Reg/Opcode (5:3) = .._.._101_...
R/M (2:0) = .._.._..._000
All other ModRM encodings are defined to be reserved, and use of these encodings risks incompatibility with future processors.
See also SFENCE and MFENCE.
EXAMPLE:
lfence