FISTP
Usage: FISTP dest Modifies flags:See below
Converts the value in the ST(0) register to a signed integer and stores the result in the 'dest' operand. Values can be stored in word or doubleword integer format. The 'dest' operand specifies the address where the first byte of the 'dest' value is to be stored, then pops the register stack.
Floating-Point/Integer Conversion
FILD mem16 ; DF /0 [8086,FPU]
FILD mem32 ; DB /0 [8086,FPU]
FILD mem64 ; DF /5 [8086,FPU]
FIST mem16 ; DF /2 [8086,FPU]
FIST mem32 ; DB /2 [8086,FPU]
FISTP mem16 ; DF /3 [8086,FPU]
FISTP mem32 ; DB /3 [8086,FPU]
FISTP mem64 ; DF /7 [8086,FPU]
FILD loads an integer out of a memory location, converts it to a real, and pushes it on the FPU register stack. FIST converts ST0 to an integer and stores that in memory; FISTP does the same as FIST, but pops the register stack afterwards.
C1 Set to 0 if stack underflow occurred. Indicates rounding direction of if the inexact exception (#P) is generated:
0 not roundup; 1 roundup.Set to 0 otherwise.
C0, C2, C3 Undefined.
EXAMPLE:
fistp Label
FIST
Usage: FIST dest Modifies flags:C1 is cleared; C0, C2, C3 undefined.
Converts the value in the ST(0) register to a signed integer and stores the result in the 'dest' operand. Values can be stored in word or doubleword integer format. The 'dest' operand specifies the address where the first byte of the 'dest' value is to be stored, then pops the register stack.
Floating-Point/Integer Conversion
FILD mem16 ; DF /0 [8086,FPU]
FILD mem32 ; DB /0 [8086,FPU]
FILD mem64 ; DF /5 [8086,FPU]
FIST mem16 ; DF /2 [8086,FPU]
FIST mem32 ; DB /2 [8086,FPU]
FISTP mem16 ; DF /3 [8086,FPU]
FISTP mem32 ; DB /3 [8086,FPU]
FISTP mem64 ; DF /7 [8086,FPU]
FILD loads an integer out of a memory location, converts it to a real, and pushes it on the FPU register stack. FIST converts ST0 to an integer and stores that in memory; FISTP does the same as FIST, but pops the register stack afterwards.
EXAMPLE:
fist Label
FINIT
Usage: FINIT Modifies flags: See below
Sets the FPU control, status, tag, instruction pointer, and data pointer registers to their default states. The FPU control word is set to 037FH (round to nearest, all exceptions masked, 64-bit precision). The status word is cleared (no exception flags set, TOP is set to 0). The data registers in the register stack are left unchanged, but they are all tagged as empty (11B). Both the instruction and data pointers are cleared.
Initialize Floating-Point Unit
FINIT ; 9B DB E3 [8086,FPU]
FNINIT ; DB E3 [8086,FPU]
FINIT initializes the FPU to its default state. It flags all registers as empty, without actually changing their values, clears the top of stack pointer. FNINIT does the same, without first waiting for pending exceptions to clear.
As the FPU Stack can not hold more than eight Values, it is good programming practice to begin each chunk of FPU Instructions with a FINIT. Even more if your Code makes use of the new SSE extensions (MMX), that also use the FPU Registers.
FPU Flags Affected C0, C1, C2, C3 set to 0.
EXAMPLE:
finit
FINCSTP
Usage: FINCSTP Modifies flags: See below.
Adds one to the TOP field of the FPU status word . If the TOP field contains a 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The FPU data registers and tag register are not affected.
Increment Floating-Point Stack Pointer
FINCSTP ; D9 F7 [8086,FPU]
FINCSTP increments the 'top' field in the floating-point status word. This has the effect of rotating the FPU register stack by one, as if the register stack had been popped, however, unlike the popping of the stack performed by many FPU instructions, it does not flag the new ST7 (previously ST0) as empty. See also FDECSTP.
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
EXAMPLE:
fincstp
FIMUL
Usage: FIMUL dest,src Modifies flags: None
Multiplies the 'dest' and 'src' operands and stores the product in the 'dest' location. The 'dest' operand is always an FPU data register; the 'src' operand can be an FPU data register or a memory location.
Floating-Point/Integer Multiplication
FIMUL mem16 ; DE /1 [8086,FPU]
FIMUL mem32 ; DA /1 [8086,FPU]
FIMUL multiplies ST0 by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in ST0.
Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.
C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
EXAMPLE:
fimul Label
FILD
Usage: FILD src Modifies flags: See below.
Converts the signed-integer 'src' operand into double extended-precision floating-point format and pushes the value onto the FPU register stack. The 'src' operand can be a word, doubleword, or quadword integer. It is loaded without rounding errors. The sign of the source operand is preserved.
Floating-Point/Integer Conversion
FILD mem16 ; DF /0 [8086,FPU]
FILD mem32 ; DB /0 [8086,FPU]
FILD mem64 ; DF /5 [8086,FPU]
FIST mem16 ; DF /2 [8086,FPU]
FIST mem32 ; DB /2 [8086,FPU]
FISTP mem16 ; DF /3 [8086,FPU]
FISTP mem32 ; DB /3 [8086,FPU]
FISTP mem64 ; DF /7 [8086,FPU]
FILD loads an integer out of a memory location, converts it to a real, and pushes it on the FPU register stack. FIST converts ST0 to an integer and stores that in memory; FISTP does the same as FIST, but pops the register stack afterwards.
C1 Set to 1 if stack overflow occurred; set to 0 otherwise.
C0, C2, C3 Undefined.
EXAMPLE:
fild st4 label
FIDIVR
Usage: FIDIVR dest,src Modifies flags:
Divides the 'src' operand by the 'dest' operand and stores the result in the 'dest' location. The 'dest' operand (divisor) is always in an FPU register; the 'src' operand (dividend) can be a register or a memory location. .
Floating-Point/Integer Division
FIDIV mem16 ; DE /6 [8086,FPU]
FIDIV mem32 ; DA /6 [8086,FPU]
FIDIVR mem16 ; DE /7 [8086,FPU]
FIDIVR mem32 ; DA /7 [8086,FPU]
FIDIV divides ST0 by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in ST0. FIDIVR does the division the other way up: it divides the integer by ST0, but still stores the result in ST0.
Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
The C0, C1, C2, and C3 are undefined.
FDIVR/FDIVRP/FIDIVR-Reverse Divide
Opcode Instruction Description
D8 /7 FDIVR m32fp Divide m32fp by ST(0) and store result in ST(0)
DC /7 FDIVR m64fp Divide m64fp by ST(0) and store result in ST(0)
D8 F8 +i FDIVR ST(0), ST(i) Divide ST(i) by ST(0) and store result in ST(0)
DC F0 +i FDIVR ST(i), ST(0) Divide ST(0) by ST(i) and store result in ST(i)
DE F0 +i FDIVRP ST(i), ST(0) Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
DE F1 FDIVRP Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
DA /7 FIDIVR m32int Divide m32int by ST(0) and store result in ST(0)
DE /7 FIDIVR m16int Divide m16int by ST(0) and store result in ST(0)
EXAMPLE:
FIDIVR ST5 ST0
FIDIV
Usage: FIDIV dest,src Modifies flags: None
Divides the 'dest' by the 'src' operand and stores the result in the 'dest'. The 'dest' (dividend) is always in an FPU register; the 'src' operand (divisor) can be a register or a memory location.
Floating-Point/Integer Division
FIDIV mem16 ; DE /6 [8086,FPU]
FIDIV mem32 ; DA /6 [8086,FPU]
FIDIVR mem16 ; DE /7 [8086,FPU]
FIDIVR mem32 ; DA /7 [8086,FPU]
FIDIV divides ST0 by the 16-bit or 32-bit integer stored in the given memory location, and stores the result in ST0. FIDIVR does the division the other way up: it divides the integer by ST0, but still stores the result in ST0.
Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0) register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location (either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The no-operand version of the floating-point divide instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.
FPU Flags Affected
C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
FDIV/FDIVP/FIDIV-Divide
Opcode Instruction Description
D8 /6 FDIV m32fp Divide ST(0) by m32fp and store result in ST(0).
DC /6 FDIV m64fp Divide ST(0) by m64fp and store result in ST(0).
D8 F0 +i FDIV ST(0), ST(i) Divide ST(0) by ST(i) and store result in ST(0).
DC F8 +i FDIV ST(i), ST(0) Divide ST(i) by ST(0) and store result in ST(i).
DE F8 +i FDIVP ST(i), ST(0) Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
DE F9 FDIVP Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
DA /6 FIDIV m32int Divide ST(0) by m32int and store result in ST(0).
DE /6 FIDIV m16int Divide ST(0) by m64int and store result in ST(0).
EXAMPLE:
fidiv st2 D$Last
FICOMP
Usage: FICOMP src Modifies flags: See below.
Compares the value in ST(0) with an integer 'src' operand and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results. The integer value is converted to double extended-precision floating-point format before the comparison is made.
Floating-Point/Integer Compare
FICOM mem16 ; DE /2 [8086,FPU]
FICOM mem32 ; DA /2 [8086,FPU]
FICOMP mem16 ; DE /3 [8086,FPU]
FICOMP mem32 ; DA /3 [8086,FPU]
FICOM compares ST0 with the 16-bit or 32-bit integer stored in the given memory location, and sets the FPU flags accordingly. FICOMP does the same, but pops the register stack afterwards.
FICOM/FICOMP Results
Condition C3 C2 C0
ST(0) >SRC 0 0 0
ST(0) <SRC 0 0 1
ST(0) =SRC 1 0 0
Unordered 1 1 1
Example:
ficomp Label
FICOM
Usage: FICOM src Modifies flags: See below
Compares the value in ST(0) with an integer 'src' operand and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). The integer value is converted to double extended-precision floating-point format before the comparison is made.
Floating-Point/Integer Compare
FICOM mem16 ; DE /2 [8086,FPU]
FICOM mem32 ; DA /2 [8086,FPU]
FICOMP mem16 ; DE /3 [8086,FPU]
FICOMP mem32 ; DA /3 [8086,FPU]
FICOM compares ST0 with the 16-bit or 32-bit integer stored in the given memory location, and sets the FPU flags accordingly. FICOMP does the same, but pops the register stack afterwards.
FICOM/FICOMP Results
Condition C3 C2 C0
ST(0) >SRC 0 0 0
ST(0) <SRC 0 0 1
ST(0) =SRC 1 0 0
Unordered 1 1 1
Example:
ficom Label