FIADD
Usage: FADD dest,src Modifies flags: None
Adds the 'dest' and 'src' operands and stores the sum in the 'dest' location. The 'dest' operand is always an FPU register; the 'src' operand can be a register or a memory location. 'Src' operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.
Floating-Point/Integer Addition
FIADD mem16 ; DE /0 [8086,FPU]
FIADD mem32 ; DA /0 [8086,FPU]
FIADD adds the 16-bit or 32-bit integer stored in the given memory location to ST0, storing the result in ST0.
C1 Set to 0 if stack underflow occurred. C0, C2, C3 Undefined.
EXAMPLE:
fiadd
fiadd st0
FFREE
Usage: FFREE src Modifies flags:
Sets the tag in the FPU tag register associated with register 'src' to empty (11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected.
Flag Floating-Point Register as Unused
FFREE fpureg ; DD C0+r [8086,FPU]
FFREEP fpureg ; DF C0+r [286,FPU,UNDOC]
FFREE marks the given register as being empty.
FFREEP marks the given register as being empty, and then pops the register stack.
C0, C1, C2, C3 undefined.
Example:
ffree st4
FEMMS
Usage: FEMMS src Modifies flags:
Faster Enter/Exit of the MMX or floating-point state
FEMMS ; 0F 0E [PENT,3DNOW]
FEMMS can be used in place of the EMMS instruction on processors which support the 3DNow! instruction set. Following execution of FEMMS, the state of the MMX/FP registers is undefined, and this allows a faster context switch between FP and MMX instructions. The FEMMS instruction can also be used executing MMX instructions
FPU Flags Affected
Example:
femms st4
FDIVRP
Usage: FDIVRP dest,src Modifies flags: None
Divides the 'dest' by the 'src' operand and stores the result in the 'dest'. The 'dest' (dividend) is always in an FPU register; the 'src' operand (divisor) can be a register or a memory location. 'Src' operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
Floating-Point Division
FDIV mem32 ; D8 /6 [8086,FPU]
FDIV mem64 ; DC /6 [8086,FPU]
FDIV fpureg ; D8 F0+r [8086,FPU]
FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
FDIV TO fpureg ; DC F8+r [8086,FPU]
FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
FDIVR mem32 ; D8 /0 [8086,FPU]
FDIVR mem64 ; DC /0 [8086,FPU]
FDIVR fpureg ; D8 F8+r [8086,FPU]
FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
FDIVR TO fpureg ; DC F0+r [8086,FPU]
FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
FDIVP fpureg ; DE F8+r [8086,FPU]
FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
FDIVRP fpureg ; DE F0+r [8086,FPU]
FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
FDIV divides ST0 by the given operand and stores the result back in ST0, unless the TO qualifier is given, in which case it divides the given operand by ST0 and stores the result in the operand.
FDIVR does the same thing, but does the division the other way up: so if TO is not given, it divides the given operand by ST0 and stores the result in ST0, whereas if TO is given it divides ST0 by its operand and stores the result in the operand.
FDIVP operates like FDIV TO, but pops the register stack once it has finished.
FDIVRP operates like FDIVR TO, but pops the register stack once it has finished.
The C0, C1, C2, and C3 are undefined.
For FP/Integer divisions, see FIDIV.
FDIVR/FDIVRP/FIDIVR-Reverse Divide
Opcode Instruction Description
D8 /7 FDIVR m32fp Divide m32fp by ST(0) and store result in ST(0)
DC /7 FDIVR m64fp Divide m64fp by ST(0) and store result in ST(0)
D8 F8 +i FDIVR ST(0), ST(i) Divide ST(i) by ST(0) and store result in ST(0)
DC F0 +i FDIVR ST(i), ST(0) Divide ST(0) by ST(i) and store result in ST(i)
DE F0 +i FDIVRP ST(i), ST(0) Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
DE F1 FDIVRP Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
DA /7 FIDIVR m32int Divide m32int by ST(0) and store result in ST(0)
DE /7 FIDIVR m16int Divide m16int by ST(0) and store result in ST(0)
EXAMPLE:
fdivrp st2 st0
FDIVR
Usage: FDIVR dest,src Modifies flags: None
Divides the 'dest' by the 'src' operand and stores the result in the 'dest'. The 'dest' (dividend) is always in an FPU register; the 'src' operand (divisor) can be a register or a memory location.
Floating-Point Division
FDIV mem32 ; D8 /6 [8086,FPU]
FDIV mem64 ; DC /6 [8086,FPU]
FDIV fpureg ; D8 F0+r [8086,FPU]
FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
FDIV TO fpureg ; DC F8+r [8086,FPU]
FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
FDIVR mem32 ; D8 /0 [8086,FPU]
FDIVR mem64 ; DC /0 [8086,FPU]
FDIVR fpureg ; D8 F8+r [8086,FPU]
FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
FDIVR TO fpureg ; DC F0+r [8086,FPU]
FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
FDIVP fpureg ; DE F8+r [8086,FPU]
FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
FDIVRP fpureg ; DE F0+r [8086,FPU]
FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
FDIV divides ST0 by the given operand and stores the result back in ST0, unless the TO qualifier is given, in which case it divides the given operand by ST0 and stores the result in the operand.
FDIVR does the same thing, but does the division the other way up: so if TO is not given, it divides the given operand by ST0 and stores the result in ST0, whereas if TO is given it divides ST0 by its operand and stores the result in the operand.
FDIVP operates like FDIV TO, but pops the register stack once it has finished.
FDIVRP operates like FDIVR TO, but pops the register stack once it has finished.
C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined.
Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
For FP/Integer divisions, see FIDIV.
FDIVR/FDIVRP/FIDIVR-Reverse Divide
Opcode Instruction Description
D8 /7 FDIVR m32fp Divide m32fp by ST(0) and store result in ST(0)
DC /7 FDIVR m64fp Divide m64fp by ST(0) and store result in ST(0)
D8 F8 +i FDIVR ST(0), ST(i) Divide ST(i) by ST(0) and store result in ST(0)
DC F0 +i FDIVR ST(i), ST(0) Divide ST(0) by ST(i) and store result in ST(i)
DE F0 +i FDIVRP ST(i), ST(0) Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
DE F1 FDIVRP Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
DA /7 FIDIVR m32int Divide m32int by ST(0) and store result in ST(0)
DE /7 FIDIVR m16int Divide m16int by ST(0) and store result in ST(0)
EXAMPLE:
fdivr st0 to st2
FDIVP
Usage: FDIVP dest,src Modifies flags: None.
Divides the 'dest' by the 'src' operand and stores the result in the 'dest'. The 'dest' (dividend) is always in an FPU register; the 'src' operand (divisor) can be a register or a memory location.
Floating-Point Division
FDIV mem32 ; D8 /6 [8086,FPU]
FDIV mem64 ; DC /6 [8086,FPU]
FDIV fpureg ; D8 F0+r [8086,FPU]
FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
FDIV TO fpureg ; DC F8+r [8086,FPU]
FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
FDIVR mem32 ; D8 /0 [8086,FPU]
FDIVR mem64 ; DC /0 [8086,FPU]
FDIVR fpureg ; D8 F8+r [8086,FPU]
FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
FDIVR TO fpureg ; DC F0+r [8086,FPU]
FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
FDIVP fpureg ; DE F8+r [8086,FPU]
FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
FDIVRP fpureg ; DE F0+r [8086,FPU]
FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
FDIV divides ST0 by the given operand and stores the result back in ST0, unless the TO qualifier is given, in which case it divides the given operand by ST0 and stores the result in the operand.
FDIVR does the same thing, but does the division the other way up: so if TO is not given, it divides the given operand by ST0 and stores the result in ST0, whereas if TO is given it divides ST0 by its operand and stores the result in the operand.
FDIVP operates like FDIV TO, but pops the register stack once it has finished.
FDIVRP operates like FDIVR TO, but pops the register stack once it has finished.
Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined.
For FP/Integer divisions, see FIDIV.
FDIV/FDIVP/FIDIV-Divide
Opcode Instruction Description
D8 /6 FDIV m32fp Divide ST(0) by m32fp and store result in ST(0).
DC /6 FDIV m64fp Divide ST(0) by m64fp and store result in ST(0).
D8 F0 +i FDIV ST(0), ST(i) Divide ST(0) by ST(i) and store result in ST(0).
DC F8 +i FDIV ST(i), ST(0) Divide ST(i) by ST(0) and store result in ST(i).
DE F8 +i FDIVP ST(i), ST(0) Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
DE F9 FDIVP Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
DA /6 FIDIV m32int Divide ST(0) by m32int and store result in ST(0).
DE /6 FIDIV m16int Divide ST(0) by m64int and store result in ST(0).
EXAMPLE:
fdivp st0 st7
FDIV
Usage: FDIV dest,src Modifies flags: None
Divides the 'dest' by the 'src' operand and stores the result in the 'dest' operand.
Floating-Point Division
FDIV mem32 ; D8 /6 [8086,FPU]
FDIV mem64 ; DC /6 [8086,FPU]
FDIV fpureg ; D8 F0+r [8086,FPU]
FDIV ST0,fpureg ; D8 F0+r [8086,FPU]
FDIV TO fpureg ; DC F8+r [8086,FPU]
FDIV fpureg,ST0 ; DC F8+r [8086,FPU]
FDIVR mem32 ; D8 /0 [8086,FPU]
FDIVR mem64 ; DC /0 [8086,FPU]
FDIVR fpureg ; D8 F8+r [8086,FPU]
FDIVR ST0,fpureg ; D8 F8+r [8086,FPU]
FDIVR TO fpureg ; DC F0+r [8086,FPU]
FDIVR fpureg,ST0 ; DC F0+r [8086,FPU]
FDIVP fpureg ; DE F8+r [8086,FPU]
FDIVP fpureg,ST0 ; DE F8+r [8086,FPU]
FDIVRP fpureg ; DE F0+r [8086,FPU]
FDIVRP fpureg,ST0 ; DE F0+r [8086,FPU]
FDIV divides ST0 by the given operand and stores the result back in ST0, unless the TO qualifier is given, in which case it divides the given operand by ST0 and stores the result in the operand.
FDIVR does the same thing, but does the division the other way up: so if TO is not given, it divides the given operand by ST0 and stores the result in ST0, whereas if TO is given it divides ST0 by its operand and stores the result in the operand.
The 'dest' (dividend) is always in an FPU register; the 'src' operand (divisor) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format, word or doubleword integer format.
FDIVP operates like FDIV TO, but pops the register stack once it has finished.
FDIVRP operates like FDIVR TO, but pops the register stack once it has finished.
For FP/Integer divisions, see FIDIV.
FDIV/FDIVP/FIDIV-Divide
Opcode Instruction Description
D8 /6 FDIV m32fp Divide ST(0) by m32fp and store result in ST(0).
DC /6 FDIV m64fp Divide ST(0) by m64fp and store result in ST(0).
D8 F0 +i FDIV ST(0), ST(i) Divide ST(0) by ST(i) and store result in ST(0).
DC F8 +i FDIV ST(i), ST(0) Divide ST(i) by ST(0) and store result in ST(i).
DE F8 +i FDIVP ST(i), ST(0) Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
DE F9 FDIVP Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
DA /6 FIDIV m32int Divide ST(0) by m32int and store result in ST(0).
DE /6 FIDIV m16int Divide ST(0) by m64int and store result in ST(0).
EXAMPLE:
fdiv st2 D$Last
FDECSTP
Usage: FDECSTP Modifies flags: None
Decrement Floating-Point Stack Pointer
FDECSTP ; D9 F6 [8086,FPU]
FDECSTP decrements the `top' field in the floating-point status word. This has the effect of rotating the FPU register stack by one, as if the contents of ST7 had been pushed on the stack. See also FINCSTP ( FINCSTP).
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.
EXAMPLE:
fdecstp
FCOS
Usage: FCOS ST0 Modifies flags: See below.
Computes the cosine of the source operand in register ST(0) and stores the result in ST(0).
Floating-Point Cosine
FCOS ; D9 FF [386,FPU]
FCOS computes the cosine of ST0 (in radians), and stores the result in ST0. The absolute value of ST0 must be less than 2**63.
See also FSINCOS ( FSIN).
FPU Flags Affected
C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise.
Undefined if C2 is 1.
C2 Set to 1 if outside range (-2**63 <source operand <+2**63 ); otherwise, set to 0.
C0, C3 Undefined.
EXAMPLE:
finit | fld st0 55.6
fcos
FCOMPP
Usage: FCOMPP src Modifies flags: See table below.
Compares contents of register ST(0) and 'src' and sets condition code flags C0, C2, and C3 in the FPU status with the results. The 'src' operand can be a data register or a memory location. If no 'src' operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is ignored, so that -0.0 is equal to to 0.
Floating-Point Compare
FCOM mem32 ; D8 /2 [8086,FPU]
FCOM mem64 ; DC /2 [8086,FPU]
FCOM fpureg ; D8 D0+r [8086,FPU]
FCOM ST0,fpureg ; D8 D0+r [8086,FPU]
FCOMP mem32 ; D8 /3 [8086,FPU]
FCOMP mem64 ; DC /3 [8086,FPU]
FCOMP fpureg ; D8 D8+r [8086,FPU]
FCOMP ST0,fpureg ; D8 D8+r [8086,FPU]
FCOMPP ; DE D9 [8086,FPU]
FCOMI fpureg ; DB F0+r [P6,FPU]
FCOMI ST0,fpureg ; DB F0+r [P6,FPU]
FCOMIP fpureg ; DF F0+r [P6,FPU]
FCOMIP ST0,fpureg ; DF F0+r [P6,FPU]
FCOM compares ST0 with the given operand, and sets the FPU flags accordingly. ST0 is treated as the left-hand side of the comparison, so that the carry flag is set (for a `less-than' result) if ST0 is less than the given operand.
FCOMP does the same as FCOM, but pops the register stack afterwards. FCOMPP compares ST0 with ST1 and then pops the register stack twice.
FCOMI and FCOMIP work like the corresponding forms of FCOM and FCOMP, but write their results directly to the CPU flags register rather than the FPU status word, so they can be immediately followed by conditional jump or conditional move instructions.
The FCOM instructions differ from the FUCOM instructions, only in the way they handle quiet NaNs: FUCOM will handle them silently and set the condition code flags to an 'unordered' result, whereas FCOM will generate an exception.
Table FCOM/FCOMP/FCOMPP Flag Results
Condition C3 C2 C0
ST(0) >SRC 0 0 0
ST(0) <SRC 0 0 1
ST(0) =SRC 1 0 0
Unordered* 1 1 1
EXAMPLE:
fcompp Label