FADD
Usage: FADD dest , src Modifies flags:
Adds the 'dest' and 'src' operands and stores the sum in the 'dest' location. The 'dest' operand is always an FPU register; the 'src' operand can be a register or a memory location. 'Src' operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.
Floating-Point Addition
FADD mem32 ; D8 /0 [8086,FPU]
FADD mem64 ; DC /0 [8086,FPU]
FADD fpureg ; D8 C0+r [8086,FPU]
FADD ST0,fpureg ; D8 C0+r [8086,FPU]
FADD TO fpureg ; DC C0+r [8086,FPU]
FADD fpureg,ST0 ; DC C0+r [8086,FPU]
FADDP fpureg ; DE C0+r [8086,FPU]
FADDP fpureg,ST0 ; DE C0+r [8086,FPU]
FADD, given one operand, adds the operand to ST0 and stores the result back in ST0. If the operand has the TO modifier, the result is stored in the register given rather than in ST0.
FADDP performs the same function as FADD TO, but pops the register stack after storing the result.
The given two-operand forms are synonyms for the one-operand forms.
The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-operand version adds the contents of a memory location (either a floating-point or an integer value) to the contents of the ST(0) register. The two operand version, adds the contents of the ST(0) register to the ST(i) register or vice versa.
To add an integer value to ST0, use the FIADD instruction.
FADD/FADDP/FIADD-Add
Opcode Instruction Description
D8 /0 FADD m32fp Add m32fp to ST(0) and store result in ST(0).
DC /0 FADD m64fp Add m64fp to ST(0) and store result in ST(0).
D8 C0 +i FADD ST(0), ST(i) Add ST(0) to ST(i) and store result in ST(0).
DC C0 +i FADD ST(i), ST(0) Add ST(i) to ST(0) and store result in ST(i).
DE C0 +i FADDP ST(i), ST(0) Add ST(0) to ST(i), store result in ST(i), and pop theregister stack.
DE C1 FADDP Add ST(0) to ST(1), store result in ST(1), and pop theregister stack.
DA /0 FIADD m32int Add m32int to ST(0) and store result in ST(0).
DE /0 FIADD m16int Add m16int to ST(0) and store result in ST(0).
EXAMPLE:
fadd Label
fadd st0
fadd st0, st0 ;Doubles the value in ST0.
FABS
Usage: FABS Modifies flags: None
Clears the sign bit of ST(0) to create the absolute value of the operand.
Floating-Point Absolute Value
FABS ; D9 E1 [8086,FPU]
FABS computes the absolute value of ST0, by clearing the sign bit, and stores the result back in ST0.
EXAMPLE:
fabs
F2XM1
Usage: F2XM1 Modifies flags: None
Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range -1.0 to +1.0. If the source value is outside this range, the result is undefined.
Calculate 2**X-1
F2XM1 ; D9 F0 [8086,FPU]
F2XM1 raises 2 to the power of ST0, subtracts one, and stores the result back into ST0. The initial contents of ST0 must be a number in the range -1.0 to +1.0.
EXAMPLE:
f2mfx1
ENTER
Usage: ENTER locals,level Modifies flags: None
Modifies stack for entry to procedure for high level language. Operand 'locals' specifies the amount of storage to be allocated on the stack. 'Level' specifies the nesting level of the routine. Paired with the LEAVE instruction, this is an efficient method of entry and exit to procedures.
Create Stack Frame
ENTER imm,imm ; C8 iw ib [186]
ENTER constructs a stack frame for a high-level language procedure call. The first operand (the iw in the opcode definition above refers to the first operand) gives the amount of stack space to allocate for local variables; the second (the ib above) gives the nesting level of the procedure (for languages like Pascal, with nested procedures).
The stack-size attribute determines whether the BP (16 bits) or EBP (32 bits) register specifies the current frame pointer and whether SP (16 bits) or ESP (32 bits) specifies the stack pointer.
The first operand (size operand) specifies the size of the stack frame (that is, the number of bytes of dynamic storage allocated on the stack for the procedure). The second operand (nesting level operand) gives the lexical nesting level (0 to 31) of the procedure. The nesting level determines the number of stack frame pointers that are copied into the 'display area' of the new stack frame from the preceding frame. Both of these operands are
immediate values.
The function of ENTER, with a nesting level of zero, is equivalent to
PUSH EBP ; or PUSH BP in 16 bits
MOV EBP,ESP ; or MOV BP,SP in 16 bits
SUB ESP,operand1 ; or SUB SP,operand1 in 16 bits
This creates a stack frame with the procedure parameters accessible upwards from EBP, and local variables accessible downwards from EBP.
With a nesting level of one, the stack frame created is 4 (or 2) bytes bigger, and the value of the final frame pointer EBP is accessible in memory at [EBP-4].
This allows ENTER, when called with a nesting level of two, to look at the stack frame described by the value of EBP, find the frame pointer at offset -4 from that, and push it along with its new frame pointer, so that when a level-two procedure is called from within a level-one procedure, [EBP-4] holds the frame pointer of the most recent level-one procedure call and [EBP-8] holds that of the most recent level-two call. And so on, for nesting levels up to 31.
Stack frames created by ENTER can be destroyed by the LEAVE instruction.
Example:
enter SframeSize NestLvl
EMMS
Usage: EMMS Modifies flags: None
Used to clear the MMX state before using registers for FPU operations.
Empty MMX State
EMMS ; 0F 77 [PENT,MMX]
EMMS sets the FPU tag word (marking which floating-point registers are available) to all ones, meaning all registers are available for the FPU to use. It should be used after executing MMX instructions and before executing any subsequent floating-point operations.
All other MMX instructions (other than the EMMS instruction) set all the tags in x87 FPU tag word to valid, all zeros. The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.
If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will result in an x87 floating-point exception or incorrect result.
EXAMPLE:
emms
DIVSS
Usage: DIVSS dest,src Modifies flags: None
Divides the low single-precision floating-point value in the 'dest' operand by the low single-precision floating-point value in the 'src' operand, and stores the single-precision floating-point result in the 'dest' operand. The 'src' operand can be an XMM register or a 32-bit memory location.
Scalar Single-Precision FP Divide
DIVSS xmm1,xmm2/mem32 ; F3 0F 5E /r [KATMAI,SSE]
DIVSS divides the low-order single-precision FP value in the destination operand by the low-order single-precision FP value in the source operand, and stores the single-precision result in the destination register.
The destination is an XMM register. The source operand can be either an XMM register or a 32-bit memory location.
dst[0-31] := dst[0-31] / src[0-31],
dst[32-127] remains unchanged.
Example:
divss xmm1 Label
DIVSD
Usage: DIVSD dest,src Modifies flags: None
Divides the low double-precision floating-point value in the 'dest' operand by the low double-precision floating-point value in the 'src' operand, and stores the double-precision floating-point result in the 'dest' operand.
Scalar Double-Precision FP Divide
DIVSD xmm1,xmm2/mem64 ; F2 0F 5E /r [WILLAMETTE,SSE2]
DIVSD divides the low-order double-precision FP value in the destination operand by the low-order double-precision FP value in the source operand, and stores the double-precision result in the destination register.
The destination is an XMM register. The source operand can be either an XMM register or a 64-bit memory location.
dst[0-63] := dst[0-63] / src[0-63],
dst[64-127] remains unchanged.
Example:
divsd xmm1 xmm2
DIVPS
Usage: DIVPS dest,src Modifies flags: None
Performs an SIMD divide of the two packed single-precision floating-point values in the 'dest' operand by the two packed single-precision floating-point values in the 'src' operand, and stores the packed single-precision floating-point results in the 'dest' operand.
Packed Single-Precision FP Divide
DIVPS xmm1,xmm2/mem128 ; 0F 5E /r [KATMAI,SSE]
DIVPS divides the two packed single-precision FP values in the destination operand by the four packed single-precision FP values in the source operand, and stores the packed single-precision results in the destination register.
The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.
dst[0-31] := dst[0-31] / src[0-31],
dst[32-63] := dst[32-63] / src[32-63],
dst[64-95] := dst[64-95] / src[64-95],
dst[96-127] := dst[96-127] / src[96-127].
Example:
divps xmm1 Label
DIVPD
Usage: DIVPD dest,src Modifies flags: None
Performs an SIMD divide of the four packed double-precision floating-point values in the 'dest' operand by the four packed double-precision floating-point values in the 'src' operand, and stores the packed double-precision floating - point results in the 'dest' operand.
Packed Double-Precision FP Divide
DIVPD xmm1,xmm2/mem128 ; 66 0F 5E /r [WILLAMETTE,SSE2]
DIVPD divides the four packed double-precision FP values in the destination operand by the two packed double-precision FP values in the source operand, and stores the packed double-precision results in the destination register.
The destination is an XMM register. The source operand can be either an XMM register or a 128-bit memory location.
dst[0-63] := dst[0-63] / src[0-63],
dst[64-127] := dst[64-127] / src[64-127].
Example:
divpd xmm1 Label
DIV
Usage: DIV src Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)
Unsigned binary division of accumulator by source.
Unsigned Integer Divide
DIV r/m8 ; F6 /6 [8086]
DIV r/m16 ; o16 F7 /6 [8086]
DIV r/m32 ; o32 F7 /6 [386]
DIV performs unsigned integer division. The explicit operand provided is the divisor; the dividend and destination operands are implicit, in the following way:
For DIV r/m8, AX is divided by the given operand; the quotient is stored in AL and the remainder in AH.
For DIV r/m16, DX:AX is divided by the given operand; the quotient is stored in AX and the remainder in DX.
For DIV r/m32, EDX:EAX is divided by the given operand; the quotient is stored in EAX and the remainder in EDX.
Signed integer division is performed by the IDIV instruction..
EXAMPLE:
AlToDecimal:
push ecx, eax
mov ecx 10
push 0-1
L1: mov ah 0 | div cl | add ah '0' | push eax | cmp al 0 | ja L1<
L2: pop eax
If eax <> 0-1
mov B$edi ah | inc edi | jmp L2<
End_If
pop eax, ecx
ret