PFRCPIT1
Usage: PFRCPIT1 dest,src Modifies flags: None
Performs the first intermediate step in the Newton-Raphson iteration to refine the reciprocal approximation produced by the PFRCP instruction (the second and final step completes the iteration and is accurate to 24 bits).
Packed Single-Precision FP Reciprocal, First Iteration Step
PFRCPIT1 mm1,mm2/m64 ; 0F 0F /r A6 [PENT,3DNOW]
PFRCPIT1 performs the first intermediate step in the calculation of the reciprocal of a single-precision FP value. The first source value mm1 is the original value, and the second source value mm2/m64 is the result of a PFRCP instruction.
For the final step in a reciprocal, returning the full 24-bit accuracy of a single-precision FP value, see PFRCPIT2. For more details, see the AMD 3DNow! technology manual.
Example:
pfrcpit1 mm1 mm2
PFRCP
Usage: PFRCP dest,src Modifies flags: None
Returns a low-precision estimate of the reciprocal of the source operand. The single result value is duplicated in both high and low halves of this instruction's 64-bit result. The source operand is single-precision with a 24-bit significand.
Packed Single-Precision FP Reciprocal Approximation
PFRCP mm1,mm2/m64 ; 0F 0F /r 96 [PENT,3DNOW]
PFRCP performs a low precision estimate of the reciprocal of the low-order single-precision FP value in the source operand, storing the result in both halves of the destination register. The result is accurate to 14 bits.
For higher precision reciprocals, this instruction should be followed by two more instructions: PFRCPIT1 and PFRCPIT2. This will result in a 24-bit accuracy. For more details, see the AMD 3DNow! technology manual.
Example:
pfrcp mm1 mm2
PFPNACC
Usage: PFPNACC dest,src Modifies flags: None
Performs mixed negative and positive accumulation of the two doublewords of the 'dest' operand and the source operand. Then stores the results in the low and high words of the 'dest' operand, respectively.
Packed Single-Precision FP Mixed Accumulate
PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW]
PFPNACC performs a positive accumulate of the two single-precision FP values in the source register and a negative accumulate of the destination register. The result of the accumulate from the destination register is stored in the low doubleword of the destination, and the result of the source accumulate is stored in the high doubleword of the destination register.
Both operands are single-precision, floating-point operands with 24-bit significands.
The operation is:
dst[0-31] := dst[0-31] - dst[32-63],
dst[32-63] := src[0-31] + src[32-63].
Example:
pfpnacc mm1 mm2
PFNACC
Usage: PFNACC dest,src Modifies flags: None
Performs negative accumulation of the two doublewords of the 'dest' operand and the 'src' operand. Then stores the results in the low and high words of the 'dest' operand.
Packed Single-Precision FP Negative Accumulate
PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW]
PFNACC performs a negative accumulate of the two single-precision FP values in the source and destination registers. The result of the accumulate from the destination register is stored in the low doubleword of the destination, and the result of the source accumulate is stored in the high doubleword of the destination register.
The operation is:
dst[0-31] := dst[0-31] - dst[32-63],
dst[32-63] := src[0-31] - src[32-63].
Both operands are single-precision, floating-point operands with 24-bit significands.
Example:
pfnacc mm1 Label
PFMUL
Usage: PFMUL dest,src Modifies flags: None
PFMUL is a vector instruction that performs multiplication of the 'dest' operand and the 'src' operand. Both operands are single-precision, floating-point operands with 24-bit significands.
Packed Single-Precision FP Multiply
PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW]
PFMUL returns the product of each pair of single-precision FP values.
dst[0-31] := dst[0-31] * src[0-31],
dst[32-63] := dst[32-63] * src[32-63].
Example:
pfmul mm2 mm1
PFMIN
Usage: PFMIN dest,src Modifies flags: None
Returns the smaller of the two single-precision, floating-point operands. Any operation with a zero and a positive number returns positive zero. An operation consisting of two zeros returns positive zero.
Packed Single-Precision FP Minimum
PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW]
PFMIN returns the lower of each pair of single-precision FP values. If the lower value is zero, it is returned as positive zero.
Example:
pfmin mm1 Label
PFMAX
Usage: PFMAX dest,src Modifies flags: None
Returns the larger of the two single-precision, floating-point operands. Any operation with a zero and a negative number returns positive zero. An operation consisting of two zeros returns positive zero.
Packed Single-Precision FP Maximum
PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW]
PFMAX returns the higher of each pair of single-precision FP values. If the higher value is zero, it is returned as positive zero.
Example:
pfmax mm1 mm2
PFCMPxx
Usage: PFCMPxx dest,src Modifies flags: None
A vector instruction that performs a comparison of the 'dest' operand and the 'src' operand and generates all one bits or all zero bits based on the result of the corresponding comparison.
Packed Single-Precision FP Compare
PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW]
PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW]
PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW]
The PFCMPxx instructions compare the packed single-point FP values in the source and destination operands, and set the destination according to the result. If the condition is true, the destination is set to all 1s, otherwise it's set to all 0s.
PFCMPEQ tests whether dest == src. PFCMPGE tests whether dest >= src.
PFCMPGT tests whether dest > src.
Example:
pfcmpeq mm1 Label | pfcmpge mm1 mm2 | pfcmpgt mm2 mm1
PFADD
Usage: PFADD dest,src Modifies flags: None
Performs mixed negative and positive accumulation of the two doublewords of the 'dest' operand and the 'src' operand. Then stores the results in the low and high words of the 'dest' operand.
Packed Single-Precision FP Addition
PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW]
PFADD performs addition on each of two packed single-precision FP value pairs.
dst[0-31] := dst[0-31] + src[0-31],
dst[32-63] := dst[32-63] + src[32-63].
Both operands are single-precision, floating-point operands with 24-bit significands.
Example:
pfadd mm1 mm2
PFACC
Usage: PFACC dest,src Modifies flags: None
Performs negative accumulation of the two doublewords of the 'dest' operand and the 'src' operand. Then stores the results in the low and high words of the 'dest' operand.
Packed Single-Precision FP Accumulate
PFACC mm1,mm2/m64 ; 0F 0F /r AE [PENT,3DNOW]
PFACC adds the two single-precision FP values from the destination operand together, then adds the two single-precision FP values from the source operand, and places the results in the low and high doublewords of the destination operand.
The operation is:
dst[0-31] := dst[0-31] + dst[32-63],
dst[32-63] := src[0-31] + src[32-63].
Both operands are single-precision, floating-point operands with 24-bit significands.
Example:
pfacc mm1 mm2