PFPNACC
Usage: PFPNACC dest,src Modifies flags: None
Performs mixed negative and positive accumulation of the two doublewords of the 'dest' operand and the source operand. Then stores the results in the low and high words of the 'dest' operand, respectively.
Packed Single-Precision FP Mixed Accumulate
PFPNACC mm1,mm2/m64 ; 0F 0F /r 8E [PENT,3DNOW]
PFPNACC performs a positive accumulate of the two single-precision FP values in the source register and a negative accumulate of the destination register. The result of the accumulate from the destination register is stored in the low doubleword of the destination, and the result of the source accumulate is stored in the high doubleword of the destination register.
Both operands are single-precision, floating-point operands with 24-bit significands.
The operation is:
dst[0-31] := dst[0-31] - dst[32-63],
dst[32-63] := src[0-31] + src[32-63].
Example:
pfpnacc mm1 mm2
PFNACC
Usage: PFNACC dest,src Modifies flags: None
Performs negative accumulation of the two doublewords of the 'dest' operand and the 'src' operand. Then stores the results in the low and high words of the 'dest' operand.
Packed Single-Precision FP Negative Accumulate
PFNACC mm1,mm2/m64 ; 0F 0F /r 8A [PENT,3DNOW]
PFNACC performs a negative accumulate of the two single-precision FP values in the source and destination registers. The result of the accumulate from the destination register is stored in the low doubleword of the destination, and the result of the source accumulate is stored in the high doubleword of the destination register.
The operation is:
dst[0-31] := dst[0-31] - dst[32-63],
dst[32-63] := src[0-31] - src[32-63].
Both operands are single-precision, floating-point operands with 24-bit significands.
Example:
pfnacc mm1 Label
PFMUL
Usage: PFMUL dest,src Modifies flags: None
PFMUL is a vector instruction that performs multiplication of the 'dest' operand and the 'src' operand. Both operands are single-precision, floating-point operands with 24-bit significands.
Packed Single-Precision FP Multiply
PFMUL mm1,mm2/m64 ; 0F 0F /r B4 [PENT,3DNOW]
PFMUL returns the product of each pair of single-precision FP values.
dst[0-31] := dst[0-31] * src[0-31],
dst[32-63] := dst[32-63] * src[32-63].
Example:
pfmul mm2 mm1
PFMIN
Usage: PFMIN dest,src Modifies flags: None
Returns the smaller of the two single-precision, floating-point operands. Any operation with a zero and a positive number returns positive zero. An operation consisting of two zeros returns positive zero.
Packed Single-Precision FP Minimum
PFMIN mm1,mm2/m64 ; 0F 0F /r 94 [PENT,3DNOW]
PFMIN returns the lower of each pair of single-precision FP values. If the lower value is zero, it is returned as positive zero.
Example:
pfmin mm1 Label
PFMAX
Usage: PFMAX dest,src Modifies flags: None
Returns the larger of the two single-precision, floating-point operands. Any operation with a zero and a negative number returns positive zero. An operation consisting of two zeros returns positive zero.
Packed Single-Precision FP Maximum
PFMAX mm1,mm2/m64 ; 0F 0F /r A4 [PENT,3DNOW]
PFMAX returns the higher of each pair of single-precision FP values. If the higher value is zero, it is returned as positive zero.
Example:
pfmax mm1 mm2
PFCMPxx
Usage: PFCMPxx dest,src Modifies flags: None
A vector instruction that performs a comparison of the 'dest' operand and the 'src' operand and generates all one bits or all zero bits based on the result of the corresponding comparison.
Packed Single-Precision FP Compare
PFCMPEQ mm1,mm2/m64 ; 0F 0F /r B0 [PENT,3DNOW]
PFCMPGE mm1,mm2/m64 ; 0F 0F /r 90 [PENT,3DNOW]
PFCMPGT mm1,mm2/m64 ; 0F 0F /r A0 [PENT,3DNOW]
The PFCMPxx instructions compare the packed single-point FP values in the source and destination operands, and set the destination according to the result. If the condition is true, the destination is set to all 1s, otherwise it's set to all 0s.
PFCMPEQ tests whether dest == src. PFCMPGE tests whether dest >= src.
PFCMPGT tests whether dest > src.
Example:
pfcmpeq mm1 Label | pfcmpge mm1 mm2 | pfcmpgt mm2 mm1
PFADD
Usage: PFADD dest,src Modifies flags: None
Performs mixed negative and positive accumulation of the two doublewords of the 'dest' operand and the 'src' operand. Then stores the results in the low and high words of the 'dest' operand.
Packed Single-Precision FP Addition
PFADD mm1,mm2/m64 ; 0F 0F /r 9E [PENT,3DNOW]
PFADD performs addition on each of two packed single-precision FP value pairs.
dst[0-31] := dst[0-31] + src[0-31],
dst[32-63] := dst[32-63] + src[32-63].
Both operands are single-precision, floating-point operands with 24-bit significands.
Example:
pfadd mm1 mm2
PF2IW
Usage: PF2IW dest,src Modifies flags: None
Converts a register containing single-precision floating-point operands to 16-bit signed integers using truncation. Arguments outside the range representable by signed 16-bit integers are saturated to the largest and smallest 16-bit integer, depending on their sign. All results are sign-extended to 32-bits.
Packed Word Integer to Single-Precision FP Convert
PI2FW mm1,mm2/m64 ; 0F 0F /r 0C [PENT,3DNOW]
PF2IW converts two signed 16-bit integers in the source operand to single-precision FP values, and stores them in the destination operand. The input values are in the low word of each doubleword.
See the PF2ID, PI2FW, and PI2FD instructions.
Example:
pf21w mm1 Label
PI2FW
Usage: PI2FW dest,src Modifies flags: None
Conversion of signed integers to single precision floating point.
Packed 16 Bit Integer to FP Conversion
PI2FW mm1, mm2/mem64 ; 0F 0F /0Ch [3DNow]
PI2FW converts a register containing signed, 16-bit integers to single-precision,
floating-point operands.
PI2FW mm1, mm2 performs the following operations:
mm1 [31:0 ] =float (mm2 [15:0 ])
mm1 [63:32 ] =float (mm2 [47:32 ])
PI2FW mm1, mem64 performs the following operations:
mmreg [31:0 ] =float (mem64 [15:0 ])
mmreg [63:32 ]=float (mem64 [47:32 ])
See also the PI2FD, PF2IW, and PF2ID instructions.
EXAMPLE:
pi2fw mm1 mm2