JCXZ
Usage: JCXZ label Modifies flags: None
Causes execution to branch to 'label' if register CX is zero. Uses unsigned comparision.
Jump if CX/ECX Zero
JCXZ imm ; a16 E3 rb [8086]
JECXZ imm ; a32 E3 rb [386]
JCXZ performs a short jump (with maximum range 128 bytes) if and only if the contents
of the CX register is 0. JECXZ does the same thing, but with ECX.
Example:
jcxz Label
Jcc
Usage: Jcc target Modifies flags: None
Checks the flags in the EFLAGS register (CF, OF, PF, SF, and ZF) and, if the flags are in the specified state (condition), performs a jump to the target instruction.
Conditional Branch
Jcc imm ; 70+cc rb [8086]
Jcc NEAR imm ; 0F 80+cc rw/rd [386]
The jump instructions execute a near (same segment) jump if and only if their conditions are satisfied. For example, JNZ jumps only if the zero flag is not set.
The ordinary form of the instructions has only a 128-byte range; the Short form is a 386 extension to the instruction set, and can span the full size of a segment.
RosAsm will not override your choice of jump instruction: if you want Jcc Long, you have to use full talking Labels (MyLabelName) and if you want the Short form, you have to make use of Local meaningless labels with short Markers (jz L2>). For having the Long form with Local Labels, you must state the the Long Form Direction marker (jz L2>>).
The SHORT upward Marker is provided for clarity, but is not necessary.
Details of the condition codes:
Flags: O S Z P C
Simple Flags tests Instructions:
je / jz . . 1 . .
jne / jnz . . 0 . .
jno 0 . . . .
jnp / jpo . . . 0 .
jnz . 0 . . .
jo 1 . . . .
jp / jpe . . . 1 .
je . 1 . . .
Unsigned Math Instructions:
jb / jnae / jc . . . . 1
jbe / jna . . 1 . 1 (both ZF and CF set on)
jnb / jae / jn . . . . 0
jnbe / ja . . 0 . 0 (both ZF and CF set off)
Signed Math Instructions:
jl / jnge A B . . . (NOT (A=B))
jle / jng A B 1 . . (NOT (A=B)) OR ZF
jnl / jge A B . . . (A=B)
jnle / jg A B 0 . .
Read j as 'jump', e as 'equal', z as 'Zeroed', n as 'not', o as 'overflow, p as 'parity', a as 'above', c as 'carry', b as 'below', g as 'greater', l as 'lower'
JE/JZ Jump if equal/Jump if zero
JNE/JNZ Jump if not equal/Jump if not zero
JAE/JNB Jump if above or equal/Jump if not below
JB/JNAE Jump if below/Jump if not above or equal
JBE/JNA Jump if below or equal/Jump if not above
JG/JNLE Jump if greater/Jump if not less or equal
JGE/JNL Jump if greater or equal/Jump if not less
JL/JNGE Jump if less/Jump if not greater or equal
JLE/JNG Jump if less or equal/Jump if not greater
JC Jump if carry
JNC Jump if not carry
JO Jump if overflow
JNO Jump if not overflow
JS Jump if sign (negative)
JNS Jump if not sign (non-negative)
JPO/JNP Jump if parity odd/Jump if not parity
JPE/JP Jump if parity even/Jump if parity
Examples:
If B$WriteCheckerWanted = &TRUE
cmp eax 32 | jnae L1>
cmp eax CR | je L1>
cmp eax ',' | jae L1>
cmp eax 8 | jbe L1>
cmp eax Tab | jne L0>
L1: call Label
IRETW
Usage: IRETW Modifies flags: AF CF DF IF PF SF TF ZF
Returns control to point of interruption by popping IP, CS and then the Flags from the stack and continues execution at this location.
Return from Interrupt
IRET ; CF [8086]
IRETW ; o16 CF [8086]
IRETD ; o32 CF [386]
IRET returns from an interrupt (hardware or software) by means of popping IP (or EIP), CS and the flags off the stack and then continuing execution from the new CS:IP.
IRETW pops IP, CS and the flags as 2 bytes each, taking 6 bytes off the stack in total.
IRETD pops EIP as 4 bytes, pops a further 4 bytes of which the top two are discarded and the bottom two go into CS, and pops the flags as 4 bytes as well, taking 12 bytes off the stack.
IRET is a shorthand for either IRETW or IRETD, depending on the default BITS setting at the time.
Example:
iretw
IRETD
Usage: IRETD Modifies flags: AF CF DF IF PF SF TF Z
Returns control to point of interruption by popping EIP, CS and then the Flags from the stack and continues execution at this location.
Return from Interrupt
IRET ; CF [8086]
IRETW ; o16 CF [8086]
IRETD ; o32 CF [386]
IRET returns from an interrupt (hardware or software) by means of popping IP (or EIP), CS and the flags off the stack and then continuing execution from the new CS:IP.
IRETW pops IP, CS and the flags as 2 bytes each, taking 6 bytes off the stack in total.
IRETD pops EIP as 4 bytes, pops a further 4 bytes of which the top two are discarded and the bottom two go into CS, and pops the flags as 4 bytes as well, taking 12 bytes off the stack.
IRET is a shorthand for either IRETW or IRETD, depending on the default BITS setting at the time.
Example:
iretd
IRET
Usage: IRET Modifies flags: AF CF DF IF PF SF TF ZF
Returns control to point of interruption by popping (E)IP, CS and then the Flags from the stack and continues execution at this location.
Return from Interrupt
IRET ; CF [8086]
IRETW ; o16 CF [8086]
IRETD ; o32 CF [386]
Returns to a program or procedure that was interrupted by an exception, an external interrupt, or a software-generated interrupt. IRET returns from an interrupt (hardware or software) by means of popping IP (or EIP), CS and the flags off the stack and then continuing execution from the new CS:IP. CPU exception interrupts will return to the instruction that cause the exception because the CS:IP placed on the stack during the interrupt is the address of the offending instruction.
IRETW pops IP, CS and the flags as 2 bytes each, taking 6 bytes off the stack in total.
IRETD pops EIP as 4 bytes, pops a further 4 bytes of which the top two are discarded and the bottom two go into CS, and pops the flags as 4 bytes as well, taking 12 bytes off the stack.
IRET is a shorthand for either IRETW or IRETD, depending on the default BITS setting at the time.
Example:
iret
INVLPG
Usage: INVLPG src Modifies flags: none
Invalidates a single page table entry in the Translation Look-Aside Buffer.
Invalidate TLB Entry
INVLPG mem ; 0F 01 /7 [486]
INVLPG invalidates the translation lookahead buffer (TLB) entry associated with the supplied memory address.
Intel warns that this instruction may be implemented differently on future processors.
Example:
invlpg Label
INVD
Usage: INVD Modifies flags: none
Flushes CPU internal cache. Issues special function bus cycle which indicates to flush external caches.Data in write-back external caches is lost.
Invalidate Internal Caches
INVD ; 0F 08 [486]
INVD invalidates and empties the processor's internal caches, and causes the processor to instruct external caches to do the same. It does not write the contents of the caches back to memory first: any modified data held in the caches will be lost. To write the data back first, use WBINVD.
Intel warns that this instruction may be implemented differently on future processors.
Example:
invd
INTO
Usage: INTO Modifies flags: IF TF
If the Overflow Flag is set this instruction generates an INT 4 which causes the code addressed by 0000:0010 in the interrupt address table (IAT) to be executed.
Interrupt if Overflow
INTO ; CE [8086]
INTO performs an INT 4 software interrupt (see INT) if and only if the overflow flag is set.
The INTO instruction raises the overflow exception, if the OF flag is set. If the flag is clear, execution continues without raising the exception. This instruction allows software to access the overflow exception handler explicitly to check for overflow conditions.
Example:
into
INT3
Usage: INT3 Modifies flags: None
Initiates a software interrupt by pushing the flags, clearing the Trap and Interrupt Flags.
Breakpoints
INT1 ; F1 [P6]
ICEBP ; F1 [P6]
INT01 ; F1 [P6]
INT3 ; CC [8086]
INT03 ; CC [8086]
INT1 and INT3 are short one-byte forms of the instructions INT 1 and INT 3 (see INT). They perform a similar function to their longer counterparts, but take up less code space. They are used as breakpoints by debuggers.
INT1, and its alternative synonyms INT01 and ICEBP, is an instruction used by in-circuit emulators (ICEs). It is present, though not documented, on some processors down to the 286, but is only documented for the Pentium Pro. INT3 is the instruction normally used as a breakpoint by debuggers.
INT3, and its synonym INT03, is not precisely equivalent to INT 3: the short form, since it is designed to be used as a breakpoint, bypasses the normal IOPL checks in virtual-8086 mode, and also does not go through interrupt redirection.
Example:
int3
INT1
Usage: INT1 Modifies flags: None
Initiates a software interrupt by pushing the flags, clearing the Trap and Interrupt Flags.
Breakpoints
INT1 ; F1 [P6]
ICEBP ; F1 [P6]
INT01 ; F1 [P6]
INT3 ; CC [8086]
INT03 ; CC [8086]
INT 3 ;CC
INT imm8 ;CD ib Interrupt vector table number
INT1 and INT3 are short one-byte forms of the instructions INT 1 and INT 3 (see INT). They perform a similar function to their longer counterparts, but take up less code space. They are used as breakpoints by debuggers.
INT1, and its alternative synonyms INT01 and ICEBP, is an instruction used by in-circuit emulators (ICEs). It is present, though not documented, on some processors down to the 286, but is only documented for the Pentium Pro. INT3 is the instruction normally used as a breakpoint by debuggers.
INT3, and its synonym INT03, is not precisely equivalent to INT 3: the short form, since it is designed to be used as a breakpoint, bypasses the normal IOPL checks in virtual-8086 mode, and also does not go through interrupt redirection.
INT 3 Interrupt 3 trap to debugger.
Example:
int1