DEC
Usage: DEC dest Modifies flags: AF OF PF SF ZF
Unsigned binary subtraction of one from the destination.
Decrement Integer
DEC reg16 ; o16 48+r [8086]
DEC reg32 ; o32 48+r [386]
DEC r/m8 ; FE /1 [8086]
DEC r/m16 ; o16 FF /1 [8086]
DEC r/m32 ; o32 FF /1 [386]
DEC subtracts 1 from its operand. It does not affect the carry flag: to affect the carry flag, use SUB something,1. DEC affects all the other flags according to the result.
This instruction can be used with a LOCK prefix to allow atomic execution.
See also INC.
Example:
pop ecx | dec ecx | cmp ecx 0 | ja LABEL
DAS
Usage: DAS Modifies flags: AF CF PF SF ZF (OF undefined)
Corrects result (in AL) of a previous BCD subtraction operation.Contents of AL are changed to a pair of packed decimal digits.
Decimal Adjustments
DAA ; 27 [8086]
DAS ; 2F [8086]
These instructions are used in conjunction with the add and subtract instructions to perform binary-coded decimal arithmetic in (one BCD digit per nibble) form. For the unpacked equivalents, see AAA.
DAA should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the AL and also the auxiliary carry flag AF, it determines whether either digit of the addition has overflowed, and adjusts it (and sets the carry and auxiliary-carry flags) if so. You can add long BCD strings together by doing ADD/DAA on the low two digits, then doing ADC/DAA on each subsequent pair of digits.
DAS works similarly to DAA, but is for use after SUB instructions rather than ADD.
Example:
das
DAA
Usage: DAA Modifies flags: AF CF PF SF ZF (OF undefined)
Corrects result (in AL) of a previous BCD addition operation. Contents of AL are changed to a pair of packed decimal digits.
Decimal Adjustments
DAA ; 27 [8086]
DAS ; 2F [8086]
These instructions are used in conjunction with the add and subtract instructions to perform binary-coded decimal arithmetic in (one BCD digit per nibble) form. For the unpacked equivalents, see AAA.
DAA should be used after a one-byte ADD instruction whose destination was the AL register: by means of examining the value in the AL and also the auxiliary carry flag AF, it determines whether either digit of the addition has overflowed, and adjusts it (and sets the carry and auxiliary-carry flags) if so. You can add long BCD strings together by doing ADD/DAA on the low two digits, then doing ADC/DAA on each subsequent pair of digits.
DAS works similarly to DAA, but is for use after SUB instructions rather than ADD.
Example:
daa
CWDE
Usage: CWDE Modifies flags: None
Converts a signed word in AX to a signed doubleword in EAX by extending the sign bit of AX throughout EAX.
Sign Extensions
CBW ; o16 98 [8086]
CWDE ; o32 98 [386]
CWD ; o16 99 [8086]
CDQ ; o32 99 [386]
All these instructions sign-extend a short value into a longer one, by replicating the top bit of the original value to fill the extended one.
CBW extends AL into AX by repeating the top bit of AL in every bit of AH. CWDE extends AX into EAX. CWD extends AX into DX:AX by repeating the top bit of AX throughout DX, and CDQ extends EAX into EDX:EAX.
EXAMPLE:
mov eax 0
mov ax 00_1111_1111_1111_1111
cwde ; eax = FFFF FFFFh
CWD
Usage: CWD Modifies flags: None
Extends sign of word in register AX throughout register DX forming a doubleword quantity in DX:AX.
Sign Extensions
CBW ; o16 98 [8086]
CWDE ; o32 98 [386]
CWD ; o16 99 [8086]
CDQ ; o32 99 [386]
All these instructions sign-extend a short value into a longer one, by replicating the top bit of the original value to fill the extended one.
CBW extends AL into AX by repeating the top bit of AL in every bit of AH. CWDE extends AX into EAX. CWD extends AX into DX:AX by repeating the top bit of AX throughout DX, and CDQ extends EAX into EDX:EAX.
EXAMPLE:
mov ax 0ffff
xor edx edx ; edx = 0
cwd ; edx = 0000 FFFF
CVTTSS2SI
Usage: CVTTSS2SI dest,src Modifies flags: None
Converts a single-precision floating-point value in the 'src' to a signed doubleword integer in the 'dest' operand.
Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
CVTTSD2SI reg32,xmm/mem32 ; F3 0F 2C /r [KATMAI,SSE]
CVTTSS2SI converts a single-precision FP value in the source operand to a signed doubleword in the destination operand. If the result is inexact, it is truncated (rounded toward zero).
The destination operand is a general purpose register. The source can be either an XMM register or a 32-bit memory location. If the source is a register, the input value is in the low doubleword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvttss2si xmm1 xmm2
CVTTSD2SI
Usage: CVTTSD2SI dest,src Modifies flags: None
Converts a double-precision floating-point value in the 'src' to a signed doubleword integer in the 'dest' operand.
Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
CVTTSD2SI reg32,xmm/mem64 ; F2 0F 2C /r [WILLAMETTE,SSE2]
CVTTSD2SI converts a double-precision FP value in the source operand to a signed doubleword in the destination operand. If the result is inexact, it is truncated (rounded toward zero).
The destination operand is a general purpose register. The source can be either an XMM register or a 64-bit memory location. If the source is an xmm register, the input value is in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvttsd2si xmm1 xmm2
CVTTPS2PI
Usage: CVTTPS2PI dest,src Modifies flags: None
Converts two packed single-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
CVTTPS2PI mm,xmm/mem64 ; 0F 2C /r [KATMAI,SSE]
CVTTPS2PI converts two packed single-precision FP values in the source operand to two packed signed doublewords in the destination operand. If the result is inexact, it is truncated (rounded toward zero). If the source is a register, the input values are in the low quadword.
The destination operand is an MMX register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the input value is in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvttps2pi xmm1 xmm2
CVTTPS2DQ
Usage: CVTTPS2DQ dest,src Modifies flags: None
Converts four packed single-precision floating-point values in the 'src' operand to four packed signed doubleword integers in the 'dest' operand.
Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
CVTTPS2DQ xmm1,xmm2/mem128 ; F3 0F 5B /r [WILLAMETTE,SSE2]
CVTTPS2DQ converts four packed single-precision FP values in the source operand to four packed signed doublewords in the destination operand. If the result is inexact, it is truncated (rounded toward zero). If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location. For more details , see the Intel Processor manuals.
Example:
cvttps2dq xmm1 Label
CVTTPD2PI
Usage: CVTTPD2PI dest,src Modifies flags: None
Converts two packed double-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
CVTTPD2PI mm,xmm/mem128 ; 66 0F 2C /r [WILLAMETTE,SSE2]
CVTTPD2PI converts two packed double-precision FP values in the source operand to two packed single-precision FP values in the destination operand. If the result is inexact, it is truncated (rounded toward zero).
The destination operand is an MMX register. The source can be either an XMM register or a 128-bit memory location. For more details , see the Intel Processor manuals.
Example:
cvttpd2pi xmm1 xmm2