CVTTPD2DQ
Usage: CVTTPD2DQ dest,src Modifies flags: None
Converts two packed double-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
CVTTPD2DQ xmm1,xmm2/mem128 ; 66 0F E6 /r [WILLAMETTE,SSE2]
CVTTPD2DQ converts two packed double-precision FP values in the source operand to two packed double-precision FP values in the destination operand. If the result is inexact, it is truncated (rounded toward zero). The high quadword is set to all 0s.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location. For more details of this see the Intel Processor manuals.
Example:
cvttpd2dq xmm1 xmm2
CVTSS2SI
Usage: CVTSS2SI dest,src Modifies flags: None
Converts a single-precision floating-point value in the 'src' to a signed doubleword integer in the 'dest' operand.
Scalar Single-Precision FP to Signed INT32 Conversion
CVTSS2SI reg32,xmm/mem32 ; F3 0F 2D /r [KATMAI,SSE]
CVTSS2SI converts a single-precision FP value from the source operand to a signed doubleword in the destination operand.
The destination operand is a general purpose register. The source can be either an XMM register or a 32-bit memory location. If the source is a register, the input value is in the low doubleword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtss2si xmm1 xmm2
CVTSS2SD
Usage: CVTSS2SD dest,src Modifies flags: None
Converts a single-precision floating-point value in the 'src' operand to a double-precision floating-point value in the 'dest' operand.
Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
CVTSS2SD xmm1,xmm2/mem32 ; F3 0F 5A /r [WILLAMETTE,SSE2]
CVTSS2SD converts a single-precision FP value from the source operand to a double-precision FP value in the low quadword of the destination operand. The high quadword is left unchanged.
The destination operand is an XMM register. The source can be either an XMM register or a 32-bit memory location. If the source is a register, the input value is contained in the low doubleword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtss2sd xmm1 xmm2
CVTSI2SS
Usage: CVTSI2SS dest,src Modifies flags: None
Converts a signed doubleword integer in the 'src' to a single-precision floating-point value in the 'dest' operand.
Signed INT32 to Scalar Single-Precision FP Conversion
CVTSI2SS xmm,r/m32 ; F3 0F 2A /r [KATMAI,SSE]
CVTSI2SS converts a signed doubleword from the source operand to a single-precision FP value in the low doubleword of the destination operand. The upper 3 doublewords are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
The destination operand is an XMM register. The source can be either a general purpose register or a 32-bit memory location. For more details, see the Intel Processor manuals.
Example:
cvtsi2ss xmm1 xmm2
CVTSI2SD
Usage: CVTSI2SD dest,src Modifies flags: None
Converts a signed doubleword integer in the 'src' to a double-precision floating-point value in the 'dest' operand.
Signed INT32 to Scalar Double-Precision FP Conversion
CVTSI2SD xmm,r/m32 ; F2 0F 2A /r [WILLAMETTE,SSE2]
CVTSI2SD converts a signed doubleword from the source operand to a double-precision FP value in the low quadword of the destination operand. The high quadword is left unchanged.
The destination operand is an XMM register. The source can be either a general purpose register or a 32-bit memory location.
For more details of this instruction, see the Intel Processor manuals.
Example:
cvtsi2sd xmm1 xmm2
CVTSD2SS
Usage: CVTSD2SS dest,src Modifies flags: None
Converts a double-precision floating-point value in the 'src' operand to a single-precision floating-point value in the 'dest' operand.
Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
CVTSD2SS xmm1,xmm2/mem64 ; F2 0F 5A /r [KATMAI,SSE]
CVTSD2SS converts a double-precision FP value from the source operand to a single-precision FP value in the low quadword of the destination operand. The upper 3 doublewords are left unchanged. When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
The destination operand is an XMM register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the input value is in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtsd2ss xmm1 xmm2
CVTSD2SI
Usage: CVTSD2SI dest,src Modifies flags: None
Converts a double-precision floating-point value in the 'src' to a signed doubleword integer in the 'dest' operand.
Scalar Double-Precision FP to Signed INT32 Conversion
CVTSD2SI reg32,xmm/mem64 ; F2 0F 2D /r [WILLAMETTE,SSE2]
CVTSD2SI converts a double-precision FP value from the source operand to a signed doubleword in the destination operand contained in the low quadword of the register.
The destination operand is a general purpose register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the input value is in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtsd2si xmm1 xmm2
CVTPS2PI
Usage: CVTPS2PI dest,src Modifies flags: None
Converts two packed single-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Single-Precision FP to Packed Signed INT32 Conversion
CVTPS2PI mm,xmm/mem64 ; 0F 2D /r [KATMAI,SSE]
CVTPS2PI converts two packed single-precision FP values from the source operand to two packed signed doublewords in the destination operand.
The destination operand is an MMX register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the input values are in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtps2pi xmm1 xmm2
CVTPS2PD
Usage: CVTPS2PD dest,src Modifies flags: None
Converts two packed single-precision floating-point values in the 'src' operand to two packed double-precision floating-point values in the 'dest' operand.
Packed Single-Precision FP to Packed Double-Precision FP Conversion
CVTPS2PD xmm1,xmm2/mem64 ; 0F 5A /r [WILLAMETTE,SSE2]
CVTPS2PD converts two packed single-precision FP values from the source operand to two packed double-precision FP values in the destination operand.
The destination operand is an XMM register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the input values are in the low quadword. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtps2pd xmm1 xmm2
CVTPS2DQ
Usage: CVTPS2DQ dest,src Modifies flags: None
Converts four packed single-precision floating-point values in the 'src' operand to four packed signed doubleword integers in the 'dest' operand.
Packed Single-Precision FP to Packed Signed INT32 Conversion
CVTPS2DQ xmm1,xmm2/mem128 ; 66 0F 5B /r [WILLAMETTE,SSE2]
CVTPS2DQ converts four packed single-precision FP values from the source operand to four packed signed doublewords in the destination operand.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location.
For more details of this instruction, see the Intel Processor manuals.
Example:
cvtpi2dq xmm1 xmm2