CVTPI2PS
Usage: CVTPI2PS dest,src Modifies flags: None
Converts two packed signed doubleword integers in the 'src' operand to two packed single-precision floating-point values in the destination operand.
Packed Signed INT32 to Packed Single-FP Conversion
CVTPI2PS xmm,mm/mem64 ; 0F 2A /r [KATMAI,SSE]
CVTPI2PS converts two packed signed doublewords from the source operand to two packed single-precision FP values in the low quadword of the destination operand. The high quadword of the destination remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register
The destination operand is an XMM register. The source can be either an MMX register or a 64-bit memory location. For more details of this instruction, see the Intel Processor manuals.
Example:
cvtpi2ps xmm1 xmm2
CVTPI2PD
Usage: CVTPI2PD dest,src Modifies flags: None
Converts two packed signed doubleword integers in the source operand to two packed double-precision floating-point values in the destination operand.
Packed Signed INT32 to Packed Double-Precision FP Conversion
CVTPI2PD xmm,mm/mem64 ; 66 0F 2A /r [WILLAMETTE,SSE2]
CVTPI2PD converts two packed signed doublewords from the source operand to two packed double-precision FP values in the destination operand.
The destination operand is an XMM register. The source can be either an MMX register or a 64-bit memory location.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PD instruction is executed.
For more details of this instruction, see the Intel Processor manuals.
Example:
cvtpi2pd xmm1 xmm2
CVTPD2PS
Usage: CVTPD2PS dest,src Modifies flags: None
Converts two packed double-precision floating-point values in the 'src' operand to two packed single-precision floating-point values in the 'dest' operand. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
Packed Double-Precision FP to Packed Single-Precision FP Conversion
CVTPD2PS xmm1,xmm2/mem128 ; 66 0F 5A /r [WILLAMETTE,SSE2]
CVTPD2PS converts two packed double-precision FP values from the source operand to two packed single-precision FP values in the low quadword of the destination operand. The high quadword of the destination is set to all 0s.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location. For more details , see the Intel Processor manuals.
Example:
cvtpd2ps xmm1 xmm2
CVTPD2PI
Usage: CVTPD2PI dest,src Modifies flags: None
Converts two packed double-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Double-Precision FP to Packed Signed INT32 Conversion
CVTPD2PI mm,xmm/mem128 ; 66 0F 2D /r [WILLAMETTE,SSE2]
CVTPD2PI converts two packed double-precision FP values from the source operand to two packed signed doublewords in the destination operand.
The destination operand is an MMX register. The source can be either an XMM register or a 128-bit memory location. The result is stored in the low quadword of the 'dest' operand, and the high quadword is cleared to all 0s. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
For more details of this instruction, see the Intel Processor manuals.
Example:
cvtpd2pi xmm1 xmm2
CVTPD2DQ
Usage: CVTPD2DQ dest,src Modifies flags: None
Converts two packed double-precision floating-point values in the 'src' operand to two packed signed doubleword integers in the 'dest' operand.
Packed Double-Precision FP to Packed Signed INT32 Conversion
CVTPD2DQ xmm1,xmm2/mem128 ; F2 0F E6 /r [WILLAMETTE,SSE2]
CVTPD2DQ converts two packed double-precision FP values from the source operand to two packed signed doublewords in the low quadword of the destination operand. The high quadword of the destination is set to all 0s.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location.
For more details of this instruction, see the Intel Processor manuals.
Example:
cvtpd2dq xmm1 xmm2
CVTDQ2PS
Usage: CVTDQ2Ps dest,src Modifies flags: None
Converts four packed signed doubleword integers in the 'src' operand to four packed single-precision floating-point values in the 'dest' operand. When a conversion is inexact, rounding is performed according to the rounding control bits in the MXCSR register.
Packed Signed INT32 to Packed Single-Precision FP Conversion
CVTDQ2PS xmm1,xmm2/mem128 ; 0F 5B /r [WILLAMETTE,SSE2]
CVTDQ2PS converts four packed signed doublewords from the source operand to four packed single-precision FP values in the destination operand.
The destination operand is an XMM register. The source can be either an XMM register or a 128-bit memory location. For more details , see the Intel Processor manuals.
Example:
cvtdq2ps xmm1 xmm2
CVTDQ2PD
Usage: CVTDQ2PD dest,src Modifies flags:
Converts two packed signed doubleword integers in the 'src' operand to two packed double-precision floating-point values in the 'dest' operand.
Packed Signed INT32 to Packed Double-Precision FP Conversion
CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2]
CVTDQ2PD converts two packed signed doublewords from the source operand to two packed double-precision FP values in the destination operand.
The destination operand is an XMM register. The source can be either an XMM register or a 64-bit memory location. If the source is a register, the packed integers are in the low quadword.
Example:
cvtdq2pd xmm1 xmm2
CPUID
Usage: CPUID Modifies flags: None
Returns processor identification and features information in the EAX, EBX, ECX, and EDX registers. The instruction's output is dependent on the contents of the EAX register upon execution.
Get CPU Identification Code
CPUID ; 0F A2 [PENT]
CPUID returns various information about the processor it is being executed on. It fills the four registers EAX, EBX, ECX and EDX with information, which varies depending on the input contents of EAX.
CPUID also acts as a barrier to serialize instruction execution: executing the CPUID instruction guarantees that all the effects (memory modification, flag modification, register modification) of previous instructions have been completed before the next instruction gets fetched.
The information returned is as follows:
If EAX is zero on input, EAX on output holds the maximum acceptable input value of EAX, and EBX:EDX:ECX contain the string 'GenuineIntel' (or not, if you have a clone processor). That is to say, EBX contains 'Genu' (in ROSASM's own sense of character constants, described in ), EDX contains 'ineI' and ECX contains 'ntel'.
If EAX is one on input, EAX on output contains version information about the processor, and EDX contains a set of feature flags, showing the presence and absence of various features. For example, bit 8 is set if the CMPXCHG8B instruction ( CMPXCHG8B) is supported, bit 15 is set if the conditional move instructions ( CMOVcc and FCMOVB) are supported, and bit 23 is set if MMX instructions are supported.
If EAX is two on input, EAX, EBX, ECX and EDX all contain information about caches and TLBs (Translation Lookahead Buffers).
For more information on the data returned from CPUID, see the documentation from Intel and other processor manufacturers.
EXAMPLE:
mov eax 1
cpuid
COMISS
Usage: COMISD src1,src2 Modifies flags:See below.
Compares the low-order single-precision FP value in the two source operands. ZF, PF and CF are set according to the result. OF, AF and AF are cleared. The unordered result is returned if either source is a NaN (QNaN or SNaN).
Scalar Ordered Single-Precision FP Compare and Set EFLAGS
COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE]
COMISS compares the single-precision floating-point values in the low doublewords of 'src' (first operand) and 'src' 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
The source1 operand is an XMM register. The source2 operand can be either an XMM register or a memory location.
The flags are set according to the following rules:
Result Flags Values
UNORDERED: ZF,PF,CF <-- 111;
GREATER_THAN: ZF,PF,CF <-- 000;
LESS_THAN: ZF,PF,CF <-- 001;
EQUAL: ZF,PF,CF <-- 100;
The COMISS instruction differs from the UCOMISS instruction in that it signals an SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN.
The UCOMISS instruction signals an invalid numeric exception only if a source operand is an SNaN. The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Example:
comiss xmm1 xmm2
COMISD
Usage: COMISD src1,src2 Modifies flags:See below.
Compares the low-order double-precision FP value in the two source operands. ZF, PF and CF are set according to the result. OF, AF and AF are cleared. The unordered result is returned if either source is a NaN (QNaN or SNaN).
Scalar Ordered Double-Precision FP Compare and Set EFLAGS
COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2]
COMISD compares the double-precision floating-point values in the low quadwords of 'src1' (first operand) and 'src' 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either 'src' operand is a NaN (QNaN or SNaN).
The source1 operand is an XMM register. The source2 operand can be either an XMM register or a memory location.
The flags are set according to the following rules:
Result Flags Values
UNORDERED: ZF,PF,CF <-- 111;
GREATER_THAN: ZF,PF,CF <-- 000;
LESS_THAN: ZF,PF,CF <-- 001;
EQUAL: ZF,PF,CF <-- 100;
The COMISD instruction differs from the UCOMISD instruction in that it signals an SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals an invalid numeric exception only if a source operand is an SNaN. The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Example:
comisd xmm1 xmm2